Proceedings of the 1994 International Conference on Parallel Processing: August 15 - 19, 1994 1. Architecture
Gespeichert in:
Körperschaft: | |
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Format: | Tagungsbericht Buch |
Sprache: | English |
Veröffentlicht: |
Boca Raton u.a.
CRC Press
1994
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Schlagworte: | |
Online-Zugang: | Inhaltsverzeichnis |
Beschreibung: | XVII, 301, 12 S. graph. Darst. |
ISBN: | 0849324939 |
Internformat
MARC
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111 | 2 | |a International Conference on Parallel Processing |n 23 |d 1994 |c Saint Charles, Ill. |j Verfasser |0 (DE-588)1400647-9 |4 aut | |
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264 | 1 | |a Boca Raton u.a. |b CRC Press |c 1994 | |
300 | |a XVII, 301, 12 S. |b graph. Darst. | ||
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Datensatz im Suchindex
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TABLE
OF
CONTENTS
VOLUME
I
-
ARCHITECTURE
Preface
.
ш
Program Committee
.
1V
Keynote Speakers
.
1V
Panel Sessions
.
v
Conference Awards
.
v
List of Referees
.
vi
Author Index
-
Full Proceedings
.
be
(R): Regular Papers
(C): Concise Papers
Session 1A: Interconnection Networks (I)
Chair
:
C.S. Raghavendra
(R): Multistage Interconnection Networks with Multiple Outlets
. 1-1
T. Hanawa, H.
Amano,
and Y. Fujikawa
(C): A High Throughput Packet-Switching Network with Neural
Network Controlled Bypass Queueing and Multiplexing
. 1-9
Y.-K. Park and G. Lee
(C): Performance Analysis of Combining Multistage Interconnection Networks
.1-13
P. Mohapatra, S. Wong, and C.R. Das
(C): A General Inside-Out Routing Algorithm for a Class of
Rearrangeable Networks
.1-17
S.-W.
Seo
and T.-y. Feng
(C): Strategies for the Massively Parallel Simulation of Interconnection Networks
.1-21
M. Jurczyk, T. Schwederski, R. Born, H.J.
Siegel,
and S. Abraham
Session 2A: Static Networks
Chair
:
A. Youssef
(R): Performance and Reliability of the Multistage Bus Network
.1-26
L.N. Bhuyan, A.K.
Nanda,
and
T. Askar
(С):
Theory of Generalized Branch and Combine Clock Networks
.1-34
A. El-Amawy and P. Kulasinghe
(C): Continuum: A Hybrid Time/Space Communications Paradigm for k-ary n-cubes
. 1-38
A.C.
Flavell and Y. Takahashi
(C): Analysis of Interconnection Networks based on Cayley Graphs
of Strong Generating Sets
. 1-42
J.-p. Huang, S. Lakshmivarahan, and S.K. Dhall
(C): A Comparative Study of Star Graphs and Rotator Graphs
.1-46
S. Ponnuswamy and V. Chaudhary
Session
ЗА:
Hierarchical Networks
Chair
:
R.C. Joshi
(R): Efficient Routing and Broadcasting in Recursive Interconnection Networks
.1-51
R.
Fernandes, D.K.
Friesen,
and A. Kanevsky
XIV
(С):
A Class of Static and Dynamic Hierarchical Interconnection Networks
. 1-59
P.T. Breznay and M.A. Lopez
(C): Designing Large Hierarchical Multiprocessor Systems under
Processor, Interconnection, and Packaging Advancements
. 1-63
D. Basak and D. K. Panda
(C): Comparison of Mesh and Hierarchical Networks for Multiprocessors
.1-67
V.C.
Hamacher
and H. Jiang
(C): Computational Properties of Mesh Connected Trees: Versatile
Architectures for Parallel Computation
. 1-72
K.
Efe
and A. Fernandez
Session 4A: Novel Architectures
Chair
:
W.E. Alexander
(R): EXECUBE
-
A New Architecture for Scalable MPPs
. 1-77
P.M.
Kogge
(R):
Programming with Functional Memory
.1-85
R. Halverson Jr. and A. Lew
(C): Dynamic Barrier Architecture for Multi-Mode Fine Grain Parallelism
Using Conventional Processors
. 1-93
W.E. Cohen, H.G. Dietz, and J.B. Sponaugle
(C): Design and Evaluation of a Multiprocessor Architecture with
Decentralized Control
. 1-97
H. Chung,
С
Wu, J. Rakes, P. J. Zievers, and Y. Lin
Session 5A: Interconnection Networks (II)
Chair
:
C.R. Das
(R): Nonblocking Operation of Asymmetrical
Clos
Networks
. 1-101
F. K. Liotopoulos and S. Chalasani
(C): A New Tag Scheme and Its Tree Representation For A Shuffle-Exchange
Network
. 1-109
T. Feng and Y. Kim
(C): On the Rearrangeability of Reverse Shuffle/Exchange Networks
.1-113
B. Park and K. Watson
(C): SNAIL: A Multiprocessor Based on the Simple Serial Synchronized
Multistage Interconnection Network Architecture
. 1-117
M. Sasahara, J. Terada, L. Zhou, K.
Gaye,
J. Yamato, S. Ogura, and H.
Amano
(С):
On Sorting Multiple Bitonic Sequences
.1-121
D. Lee and
К. Е.
Batcher
Session 6A:
Wormhole
Routing
Chair
:
H.J.
Siegel
(R):
Sequencing of Concurrent Communication Traffic in a Mesh
Multicomputer with Virtual Channels
. 1-126
B.-r. Tsai and K.G. Shin
(R): Optimal Multicast Communication in a Wormhole-Routed Torus Networks
. 1-134
D.F. Robinson, P.K.
McKinley,
and
B.H.C.
Cheng
xv
(R): A
Necessary and Sufficient Condition for Deadlock-Free
Adaptive Routing in
Wormhole
Networks
.1-142
J. Duato
Session 7A: Cache (I)
Chair
:
J. Baer
(R): A Distributed Cache Coherence Protocol for Hypercube Multiprocessors
.1-150
Y. Chang, L.N. Bhuyan, and A. Kumar
(R): An Integrated Methodology for the Verification of Directory-Based
Cache Protocols
. 1-158
F. Pong, P.
Stenström,
and
M. Dubois
(R):
Reducing the Write Traffic for a Hybrid Cache Protocol
. 1-166
F.
Dahlgren
and P.
Stenström
Session 8A: Communication Issues
Chair
:
K. Batcher
(R): Latency Analysis of CC-NUMA and CC-COMA Rings
. 1-174
X. Zhang and Y. Yan
(C): Compiling Functional Parallelism on a Family of Different
Distributed Memory Architectures
. 1-182
S.
Pande
and K. Psarris
(C): Deadlock Free Asynchronous Communication Strategies for Unstructured
Computations on iPSC/860
. 1-187
S. Venugopal and V.K. Naik
(C): A Comparative Performance Study of an Interconnection Cached Network
.1-191
V. Gupta and E. Schenfeld
(C): Hybrid Multiprocessing in
"OPTIMUL":
A Multiprocessor For Distributed and
Shared Memory Multiprocessing with WDM Optical Fiber Interconnections
.1-196
K. Ghose, R.K. Horsell, and
N.
Singhvi
Session 9A: Memory Systems
Chair
:
M.S. Yousif
(R): A Shared Memory Environment for Hypercubes
.1-200
A. Agarwala and C.R. Das
(C): Optimizing IPC Performance for Shared-Memory Multiprocessors
. 1-208
B. Gamsa, O.
Krieger
and M.
Stumm
(R):
Module Partitioning and Interlaced Data Placement Schemes to
Reduce Conflicts in Interleaved Memories
. 1-212
L. Kurian, B. Choi, P.T. Hulina and L.D. Coraor
(C):
PSIM:
Periodically Shifted Interleaved Memory System
.1-220
J. Y. Lee and H. Y. Youn
Session 10A: VLSI Based Architecture
Chair
:
A. Dahbura
(R): An Efficient VLSI Architecture for Template Matching
. 1-224
N.
Ranganathan and S. Venugopal
XVI
(С):
Block Data Processing using Commercial Processors
. 1-232
K.N. Ellis and W.E. Alexander
(C): Rank Order Filtering on an Array With Faulty Processors
.1-236
J. Salinas and F.
Lombardi
(С):
Image Correlation: A Case Study to Examine SIMD/MIMD
Trade-offs for Scalable Parallel Algorithms
.1-241
J.B. Armstrong, M.A. Nichols, H.J.
Siegel,
and K.H. Casey
(C): Fault-Tolerant Routing Algorithms for a Massively Parallel Machine
.1-246
C. Aktouf,
C. Róbach,
and G.
Mazare
Session 11A: Cache (II)
Chair
:
L.N. Bhuyan
(R): A One's Complement Cache Memory
. 1-250
Q. Yang and S.
Adina
(С):
Can High Bandwidth and Latency Justify Large Cache Blocks in
Scalable Multiprocessors?
. 1-258
R.
Bianchina
and T.J. LeBlanc
(C): Compiler Optimization Technique for Data Cache Prefetching Using
a Small CAM Array
. 1-263
C.H. Chi
(C): Degenerate Sharing
. 1-267
R. L. Hyde and B. D.
Fleisch
(С):
Error Recovery in Parallel Systems of Pipelined Processors with Caches
. 1-271
J.P. Lin, S.C. Wang, and S.Y. Kuo
Session 12A: Multithreading/VLIW
Chair
:
C.L. Wu
(R): Performance of Switch Blocking on Multithreaded Architectures
.1-275
K. Gopinath, Krishna Narasimhan M.K., B.H.
Lim,
and A. Agarwal
(R): An Analytical Approach to Scheduling Code for Superscalar and
VLIW Architectures
. 1-285
S.K. Chen, W.K.
Fuchs,
and W.M.W. Hwu
(C): Performance Issues of a Superscalar Microprocessor
. 1-293
S. Wallace and
N.
Bagherzadeh
(C): Partitioning of Variables for Multiple-Register-File VLIW Architectures
. 1-298
A. Capitanio,
N. Dutt,
and
Α.
Nicolau
Table of Contents
-
Full Proceedings
.
Al
XVII |
any_adam_object | 1 |
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spelling | International Conference on Parallel Processing 23 1994 Saint Charles, Ill. Verfasser (DE-588)1400647-9 aut Proceedings of the 1994 International Conference on Parallel Processing August 15 - 19, 1994 1. Architecture Dharma P. Agrawal ... ed. Boca Raton u.a. CRC Press 1994 XVII, 301, 12 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier (DE-588)1071861417 Konferenzschrift gnd-content Agrawal, Dharma P. 1945- Sonstige (DE-588)11564587X oth (DE-604)BV009986785 1. Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006618807&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
spellingShingle | Proceedings of the 1994 International Conference on Parallel Processing August 15 - 19, 1994 |
subject_GND | (DE-588)1071861417 |
title | Proceedings of the 1994 International Conference on Parallel Processing August 15 - 19, 1994 |
title_auth | Proceedings of the 1994 International Conference on Parallel Processing August 15 - 19, 1994 |
title_exact_search | Proceedings of the 1994 International Conference on Parallel Processing August 15 - 19, 1994 |
title_full | Proceedings of the 1994 International Conference on Parallel Processing August 15 - 19, 1994 1. Architecture Dharma P. Agrawal ... ed. |
title_fullStr | Proceedings of the 1994 International Conference on Parallel Processing August 15 - 19, 1994 1. Architecture Dharma P. Agrawal ... ed. |
title_full_unstemmed | Proceedings of the 1994 International Conference on Parallel Processing August 15 - 19, 1994 1. Architecture Dharma P. Agrawal ... ed. |
title_short | Proceedings of the 1994 International Conference on Parallel Processing |
title_sort | proceedings of the 1994 international conference on parallel processing august 15 19 1994 architecture |
title_sub | August 15 - 19, 1994 |
topic_facet | Konferenzschrift |
url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006618807&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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