Proceedings of the 4th International Symposium on Power Semiconductor Devices & ICs: ISPSD'92 ; May 19 - 21, 1992, Waseda University, Tokyo, Japan
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| Format: | Conference Proceeding Book |
| Language: | Undetermined |
| Published: |
Tokyo
Inst. of Electrical Engineers
1992
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| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XIII, 344 S. Ill., graph. Darst. |
| ISBN: | 0780308131 078030814X 0780308158 |
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| 111 | 2 | |a International Symposium on Power Semiconductor Devices & ICs |n 4 |d 1992 |c Tokio |j Verfasser |0 (DE-588)5076820-7 |4 aut | |
| 245 | 1 | 0 | |a Proceedings of the 4th International Symposium on Power Semiconductor Devices & ICs |b ISPSD'92 ; May 19 - 21, 1992, Waseda University, Tokyo, Japan |
| 264 | 1 | |a Tokyo |b Inst. of Electrical Engineers |c 1992 | |
| 300 | |a XIII, 344 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
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| adam_text | TABLE
OF
CONTENTS
Session
1:
Plenary
Session
(Invited Papers)
Tuesday, May
19, 9: 35 - 11 :05
Chairpersons: Y. Uchida, Fuji Electric Co., Ltd.
B.J.
Baliga,
North Carolina State University
1.1
Power Electronics in Maglev Transport (Invited)
2
E.
Masada,
The University of Tokyo, Japan
1.2
Non
destructive Measurements for Analyzing Power Semiconductor
8
Devices (Invited)
P.R. Palmer, CM. Johnson, University of Cambridge, UK
1.3
Issues in Computer Aided Engineering for Power Semiconductor
15
Devices and ICs (Invited)
R.K. Williams, Siliconix Inc., USA
Session
2:
IGBTs
Tuesday, May
19, 11 : 15 - 12 : 30
Chairpersons: H.Kondoh,
M
its
ubis i
Electric Corp.
G.Charitat, LASS
/CNRS
2.1
Static and Dynamic Characteristics of High Voltage (3.5kV) IGBT
22
and MCT Devices
F. Bauer, T. Stockmeier, H.
Lendenmann*,
H.
Dettmer* and W.
Rehmer*
Asea
Brown Boveri Ud., Switzerland, *Swiss Fed. lnst. of Technology, Switzerland
2.2
Double Gate
MOS
Device Having IGBT and MCT Performances
28
S. Momota, M. Otsuki and K. Sakurai, Fuji Electric Co., Ltd., Japan
2.3
A Study on IGBT s Steady State
SOA
with Newly Developed Simulation
34
K. Nakayama and A. Nakagawa, Toshiba Corp., Japan
VI
Session 3: Power ICs (
I
)
Tuesday, May
19, 13 : 45 - 15 : 25
Chairpersons:
Y. Sugawara,
Hitachi Ltd.
D. Paxman, Philips Research Lab.
3.1
Comparison of
DI and
JI
Lateral IGBTs
40
Y.S. Huang, B.J.
Baliga,
S. Tandon
and
Α.
Reisman,
North Carolina State University, USA
3.2
A Versatile Linkage Device for High -Voltage IC s
44
A.
Bodensohn,
J. Korec
and
D.Silber*,
Daimler
Benz
AG.,
Germany,
*University
of Bremen, Germany
3.3
Fast Switching LIGBT Devices Fabricated in SOI Substrates
48
D. Disney and J.
Plummer,
Stanford University, USA
ЪА
A Novel DMOS Structure for
1.5
μ
m
Rule Bi-CDMOS Process
52
N.
Fujishima, Y. Yano and K. Tsuchiya, Fuji Electric Co., Ltd., Japan
Session
4;
Diodes
Tuesday, May
19, 15 : 35 - 17 :40
Chairpersons: H. Shigekane, Fuji Electric Co., Ltd.
Y. Choi, Ajou Uiversity
4.1
High Voltage (4kV) Emitter Short Type Diode
(ESD)
60
M.
Kitagawa,
К.
Matsushita and A. Nakagawa, Toshiba Corp., Japan
4.2
The Low Power Dissipation Schottky Barrier Diode
66
with Trench Structure
S. Kunori, J. Ishida, M. Tanaka, M. Wakatabe and T. Kan
Shindengen Electric Mfg. Co., Ltd., Japan
4.3
Channel Diode, a New Fast Switching Power Diode
72
H.P. Yee, P.O.
Lauritzen
and
S.S.
Yee, University of Washington, USA
4.4
Low Leakage Current Schottky Barrier Diode
80
H.
Kozaka,
M.
Takata,
S.
Murakami and T. Yatsuo, Hitachi Ltd., Japan
4.5
High-Voltage Termination Using Enhanced Surface Doping
86
L.E. Clark, R.B. Davies and P.J.
Groenig,
Motorola Inc., USA
Session 5:
High Voltage Bipolar Devices
Wednesday, May
20, 9 : 30 - 10 : 45
Chairpersons:
T. lida,
Okayama University of Science
R.
Sittig,
Technical University of Braunschweig
5.1
A Normally-Off Bipolar Mode Static Induction Transistor
(ВЅГГ)
92
with High Current Gains
M. Ishiko. S. Kawaji, H. Tadano, S. Sugiyama and H. Takagi*
Toyota Central Labs. Inc., Japan, Toyota Automatic Loom Works Ltd., Japan
5.2
Formation of High Quality Epitaxial Layer for an Improved GTO
98
M. Watanabe, Y. Takahashi, O. Yamada, S.
Tagami
and H. Kirihata
Fuji Electric Co., Ltd., Japan
5.3
A New Concept
,
OverVoltage Self-Protected
Thyristor 104
Y.
Shimizu,
S.
Murakami,
M.
Takata
and H. Honma,
Hitachi Ltd., Japan
Session
6:
Modeling
&
Simulation
Wednesday, May
20, 10 : 55 - 12 : 35
Chairpersons: A. Nakagawa, Toshiba Corp.
C.A.T.
Salama,
University of Tronto
6.1
4.5kV
GTO Turn-off Failure Analysis under an Inductive Load Including
112
Snubber, Gate Circuit and Various Parasitics
I. Omura and A. Nakagawa, Toshiba Corp., Japan
6.2
Failure Prediction of Power Devices under Reverse Surge Current Conditions
118
B. Freydin, E.
Veimre*
and
A. Udal*,
Si/vaco
International, USA,
Tallinn Technical University, Estonia
6.3
Modelling the Self-Heating of Power Devices
124
R.
Kraus,
P. Tiirkes* and H.J. Mattausch*. University of
Bundeswehr
Munich, Germany,
*Siemens
AG,
Germany
6.4
Full Dynamic Power Diode Model Including Temperature
130
Behavior for Use in Circuit Simulators
H. Goebel and K. Hoffmann, University of
Bundeswehr
Munich, Germany
VI
Session 7: Power MOSFETs
Wednesday, May
20, 13 : 45 - 15 : 00
Chairpersons:
К.
Sekine, Science
University of
Tokyo
T.P. Chow,
Rensselar
Polytechnic
Institute
7.1
A Novel Schottky Junction
Back Gate VDMOSFET 138
N. Yamashita, E.S. Vera, T. Sakai and T. Yachi,
NTT Corp.,
Japan
7.2 An Intelligent
Discrete
Power MOSFET
with Shorted Load Protection Using
144
Thin-Film Bipolar Transistor
K. Throngnumchai, Nissan Motor Co., Ltd., Japan
7.3
A
30-
V/75-m
Ω
.
mm2 Power MOSFET for Intelligent Driver LSIs
150
M. Morikawa, K. Sakamoto, K. Uchida,
T. Koda, K.
Satonaka and I. Yoshida
Hitachi Ltd., Japan
Session
8:
Late News
Wednesday, May
20, 15 : 10 - 16 : 10
Chairpersons: H. Ohashi, Toshiba Corp.
N.
Haneji, Yokohama National University
8.1
Highly Efficient 1.5GHz Si Power MOSFET for Digital Cellular Front End
156
I. Yoshida, M. Katsueda, S. Ohtaka, Y. Maruyama and T. Okabe, Hitachi Ltd., Japan
8.2
Electrothermal Simulation of an IGBT
158
V. Axelrad and R. Klein*, Technology Modeling Associates, USA
,
^Laboratoire
ď
Electronique de Technologie, France
8.3
On-Chip New
Current Sensing
Technology
with High Accuracy Using
160
Field Effect Resistance for Intellgnet Power MOSFETs
N.
Tokura, T. Yamamoto and K.
Hara,
Nippondenso Co., Ltd., Japan
Session
9:
Poster Session
Wednesday, May
20, 16 : 30 - 18 : 30
9.1
Compact GTO-A New Gate Turn-off
Thyristor
Design for Improved Safe
164
Operating Area
M. Bakowski, M.
Ljungberg
,
H.
Elderstig and P. Norlin
Swedish Institute of Microelectronics, Sweden
9.2
A New Generation High Speed Low Loss IGBT Module
168
G. Majumdar, J. Yamashita, H. Nishihara, Y. Tomomatsu,
N.
Soejima, M. Tabata and H. Hagino
Mitsubishi Electric Corp., Japan
9.3
Study of the
Resurf
Principle for Thin Epitaxial Layer High Voltage
172
Integrated Circuits
E.M.S. Narayanan, G. Amaratunga and W.I. Milne, Cambridge University, U.K.
9.4
Numerical Analysis of Turn-off Behavior of IGBT with an Inductive Load
176
N.
Iwamuro, Fuji Electric Co., Ltd., Japan
9.5
4.5kV, 3000A Reverse Conducting GTO
Thyristor
(R-C GTO)
180
T. Nakagawa, F. Tokunoh, Y. Yamauchi, M. Yamamoto and K.Niinobu
Mitsubishi Electric Corp., Japan
9.6
A Process Oriented VDMOSFET Model for Circuit Simulation
184
W.
Soppa
and
J. Hänseler,
Siemens
AG,
Germany
9.7
Cryogenic Operation of Asymmetric
η
-Channel IGBTs
188
R. Singh and B.J.
Baliga
North Carolina State University, USA
9.8
Gate Operation Circuit Configuration with a Power Supply for MOS-Gate
194
Devices
N.
Kumagai, Fuji Electric Co., Ltd., Japan
9.9
Application of a New Fabrication Technique to GaAs SIThy using LPE
198
A. Tornita,
T.
Kamiya,
M.
Kimura, A. Tanaka and T. Sukegawa,
Shizuoka
University, Japan
9.10
A Design Methodology for the Minimum Die Area of Power MOSFET s
202
Considering Thermal Resistance of the Package
I.J. Kim, S.K. Hwang, Y.I. Choi
*
and M.K. Han, Seoul Nafl University, Korea,
*Ajou University, Korea
9.11
High Voltage IGBT with a New Semi-Resistive Film Over Edge Structure
206
R. Saitoh, A. Nishiura and K. Sakurai, Fuji Electric Co., Ltd., Japan
9.12
A Novel GTO
Thyristor
Structure
211
A. Silard, S. Cercelaru, M.
Dut,ã,
F.
Udrea,
F.
Crăciunoiu*
and M.
Mărgărit*
Polytechnic
Institute,
Romania,
CCSÏT-CE
.Romania
9.13
A New Junction Termination Technique for Power Devices:
213
RESURF LDMOS
with
SIPOS
Layers
G. Charitat, M.A. Bouanane and P.
Rossel
Laboratoire
ď
Automatique et
ď
Analyse des Systèmes, France
9.14
Progress towards a MCT-based High Frequency Capacitor Power Supply
217
C.C.G.
Braun
and J. Carter, U.SArmy LABCOM, USA
9.15
Optimum Driving Circuit for IGBT Devices Suitable for Integration
221
С
Licitra, S. Musumeci, A. Raciti, A. Galluzzo*,
R. Letor*
and M. Melito*
Universita
di
Catania, Italy, *SGS-Thomson Microelectronics, Italy
9.16
Improvement in On-Resistance of a High-Purity Channel
ЅГГ
by a Shielded
226
Gate Structure
K. Yano, C.W. Kim, M. Kimura, A. Tanaka, S. Motoyama* and T. Sukegawa
Shizuoka
University, Japan, *New Japan Radio Co., Ltd., Japan
9.17
Comparison between Biased and Floating Guard Rings
230
Used as Junction Termination Technique
V. Macary, G. Charitat*, M. Bafleur*, J.
Buxo*
and P.
Rossel*
Motorola Semiconducteurs, France,
*Laboratoire
ď
Automatique et d Analyse des Systèmes, France
9.18
Temperature Dependence of Gummel-Poon Model Parameters
234
from
- 40
^
T
^
185
X, for Medium-Voltage, Junction-Isolated BJT s
A. Bhalla, T.P. Chow and M.K. Chen*, Rensselaer Polytechnic Institute, USA
,
*Delco Electronics Corp., USA
9.19
WITHDRAWN
9.20
Power MOSFET with Hold-Type Thennal Shutdown Function (Late News)
238
K. Sakamoto, I. Yoshida, S. Ohtaka and H. Tsunoda, Hitachi Ltd., Japan
9.21
Low-Temperature SOI Wafer Bonding (Late News)
240
F. Sugimoto and Y. Arimoto, Fujitsu Laboratories Ltd., Japan
9.22
Comparison of Junction-Isolated and SOI High-Voltage
242
Devices Operating in the Source-Follower Mode (Late News)
E. Arnold, S. Merchant, M.
Amato,
S.
Mukherjee,
H.
Pein
and A. Ludikhuize*,
Philips Laboratories, USA,
*
Philips Research Laboratories, Netherlands
9.23
Optimization of 500V, P-Channel VDMOS-LIGBT Transistors (Late News)
244
V. Parthasarathy and T.P. Chow, Rensselaer Polytechnic Institute, USA
9.24
Thermal Dissipation of Chip on Chip Module (Late News)
246
K. Kodama, T.
Akai,
M.
Mizukoshi and T. Yamauchi, Fujitsu Co., Ltd., Japan
9.25
Modeling and Optimization of Semi-Insulator
Passivated
High-Voltage
248
Field Plate Devices (Late News)
C.B. Goud
and K.N. Bhat, Indian Institute of Technology, India
9.26 Expression
for I-V Forward Characteristic of MCTs (Late News)
250
D. Czarkowski and M.K. Kazimierczuk, Wright State University, USA
9.27
Failure in GTO Circuits due to the Change in Recovery Characteristic
252
of Snubber Diodes (Late News)
P.T. Hoban, M.
Carreira
and N.Y.A Shammas, Staffordshire Polytechnic, UK
Session
10:
MOS
Gate
Thyristors
Thursday, May
21, 9: 30 - 10 : 45
Chairpersons: K. Muraoka, Toyo Electric MFC Co., Ltd.
A.A.
Jaecklin,
Asea
Brown Boveri Research Center
10.1
Fast Switching Power MOS-gated (EST/BRT)
Thyristors 256
M.
Nandakumar, M.S. Shekar and B.J.
Baliga,
North Carolina State University, USA
10.2
The FiBS, a New High Voltage BiMOS Switch
261
K. Lilja
and
T. Stockmeier, Asea
Brown Boveri Ltd., Switzerland
10.3
MOS
Controlled Current Interruption as a Turn off Mechanism for
Thyristors 266
Q.
Huang, G.A.J. Amaratunga and W. Milne, University of Cambridge, UK
Session
11 :
Power ICs
(
Π
)
Thursday, May
21, 10: 55 - 12 : 35
Chairpersons: Y. Arimoto, Fujitsu Lab. Ltd.
C. Contiero, SGS-Thomson Microelectonics
11.1
Simulation of a 700V High-Voltage Device Structure on a Thin SOI
272
-Substrate Bias Effect on SOI Devices-
T. Matsudai and A. Nakagawa, Toshiba Corp., Japan
11.2
A New Concept for High -Voltage SOI Devices
278
W. Wondrak, R. Held, E. Stein and
J. Korec,
Daimler-Benz
,
Germany
11.3
Electrothermal Circuit Simulation of Power ICs Combining SPICE
282
and
3D
Finite Element Analysis
R.K. Williams, M. Rodamaker and L.T.
Sevilla,
Siliconi*,
Inc., USA
11.4
Modeling and Characterization of
SIPOS Passivated,
High Voltage,
288
η
-and p-Channel Lateral
RESURF Type
DMOSFETs
T. Sakai, K.C. So, Z. Shen and T.P. Chow, Rensselaer Polytechnic Institute, USA
Хй
Session 12: Power
MOS
/
MES FETs
Thursday, May
21, 13 : 45 - 15 : 25
Chairpersons:
T. Sakai,
NTT Applied Electronics Lab.
M.A. Shibib, AT
&
T Bell
Lab.
12.1
A Novel Power MOSFET Using Drain Trench Technology
294
E.S.
Vera, N.
Yamashita and T. Yachi, NTT Corp., Japan
12.2
A Study on a High Blocking Voltage UMOS-FET with a Double Gate Structure
300
Y. Baba,
N.
Matsuda, S. Yanagiya, S. Hiraki and S. Yasuda, Toshiba Corp., Japan
12.3
Effect of Contact Resistivities and Interface Properties on the Performance
303
of SiC Power Devices
Т.К.
Wang, T.P. Chow,
D.M.
Brown* and M. Ghezzo*
Rensselaer Polytechnic Institute, USA
,
^General Electric Corp., USA
VIA High-Voltage High-Speed MESFETs Using a Standard GaAs Digital
1С
Process
309
P.K.T.
Mok
and C.A.T.
Salarna,
University of Toronto, Canada
Session
13:
Applications
Thursday, May
21, 15 : 35 - 17 : 40
Chairpersons: T.
Usui,
Oki
Electric Industry Co., Ltd.
R. Williams, Silikonix Inc.
13.1
New Dielectric Isolation for High Voltage Power ICs by Single Silicon Poly
316
Silicon Direct Bonding (SPSDB) Technique
Y. Sugawara, Y. Inoue, S. Ogawa and S. Kurita*
Hitachi Ltd., Japan, Hitachi Haranomachi Denshi, Japan
13.2
A 1200V BiCMOS Technology and its Applications
322
V. Rumennik, Power Integrations, Inc., USA
13.3
500V Three Phase Inverter ICs Based on a New Dielectric Isolation Technique
328
A. Nakagawa, Y. Yamaguchi, T. Ogura, K. Watanabe, Y. Yasuhara, R. Sato,
K. Endo and K. Furukawa, Toshiba Corp., Japan
13.4
A Planar 2500V
0.3
A Bipolar Transistor for High Voltage Control Circuit
333
M. Nagata, Y. Koike, S. Okada and M. Shigeta, SANYO Electric Co., Ltd., Japan
13.5
Power MOSFET Analysis
/
Optimization for Cryogenic Operation Including
339
the Effect of Degradation in Breakdown Voltage
R. Singh and B.J.
Baliga,
North Carolina State University, USA
|
| any_adam_object | 1 |
| author_corporate | International Symposium on Power Semiconductor Devices & ICs Tokio |
| author_corporate_role | aut |
| author_facet | International Symposium on Power Semiconductor Devices & ICs Tokio |
| author_sort | International Symposium on Power Semiconductor Devices & ICs Tokio |
| building | Verbundindex |
| bvnumber | BV009527555 |
| classification_tum | ELT 318f |
| ctrlnum | (OCoLC)633268213 (DE-599)BVBBV009527555 |
| discipline | Elektrotechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 1992 Tokio gnd-content |
| genre_facet | Konferenzschrift 1992 Tokio |
| id | DE-604.BV009527555 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T17:36:32Z |
| institution | BVB |
| institution_GND | (DE-588)5076820-7 |
| isbn | 0780308131 078030814X 0780308158 |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006291008 |
| oclc_num | 633268213 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-83 |
| owner_facet | DE-91 DE-BY-TUM DE-83 |
| physical | XIII, 344 S. Ill., graph. Darst. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| publisher | Inst. of Electrical Engineers |
| record_format | marc |
| spelling | International Symposium on Power Semiconductor Devices & ICs 4 1992 Tokio Verfasser (DE-588)5076820-7 aut Proceedings of the 4th International Symposium on Power Semiconductor Devices & ICs ISPSD'92 ; May 19 - 21, 1992, Waseda University, Tokyo, Japan Tokyo Inst. of Electrical Engineers 1992 XIII, 344 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Leistungselektronik (DE-588)4035235-3 gnd rswk-swf Elektronisches Bauelement (DE-588)4014360-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1992 Tokio gnd-content Elektronisches Bauelement (DE-588)4014360-0 s Leistungselektronik (DE-588)4035235-3 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006291008&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings of the 4th International Symposium on Power Semiconductor Devices & ICs ISPSD'92 ; May 19 - 21, 1992, Waseda University, Tokyo, Japan Leistungselektronik (DE-588)4035235-3 gnd Elektronisches Bauelement (DE-588)4014360-0 gnd |
| subject_GND | (DE-588)4035235-3 (DE-588)4014360-0 (DE-588)1071861417 |
| title | Proceedings of the 4th International Symposium on Power Semiconductor Devices & ICs ISPSD'92 ; May 19 - 21, 1992, Waseda University, Tokyo, Japan |
| title_auth | Proceedings of the 4th International Symposium on Power Semiconductor Devices & ICs ISPSD'92 ; May 19 - 21, 1992, Waseda University, Tokyo, Japan |
| title_exact_search | Proceedings of the 4th International Symposium on Power Semiconductor Devices & ICs ISPSD'92 ; May 19 - 21, 1992, Waseda University, Tokyo, Japan |
| title_full | Proceedings of the 4th International Symposium on Power Semiconductor Devices & ICs ISPSD'92 ; May 19 - 21, 1992, Waseda University, Tokyo, Japan |
| title_fullStr | Proceedings of the 4th International Symposium on Power Semiconductor Devices & ICs ISPSD'92 ; May 19 - 21, 1992, Waseda University, Tokyo, Japan |
| title_full_unstemmed | Proceedings of the 4th International Symposium on Power Semiconductor Devices & ICs ISPSD'92 ; May 19 - 21, 1992, Waseda University, Tokyo, Japan |
| title_short | Proceedings of the 4th International Symposium on Power Semiconductor Devices & ICs |
| title_sort | proceedings of the 4th international symposium on power semiconductor devices ics ispsd 92 may 19 21 1992 waseda university tokyo japan |
| title_sub | ISPSD'92 ; May 19 - 21, 1992, Waseda University, Tokyo, Japan |
| topic | Leistungselektronik (DE-588)4035235-3 gnd Elektronisches Bauelement (DE-588)4014360-0 gnd |
| topic_facet | Leistungselektronik Elektronisches Bauelement Konferenzschrift 1992 Tokio |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006291008&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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