Balance in architectural design:
We introduce a performance metric, normalized time, which is closely related to such measures as the area-time product of very large scale integration theory, and the price/performance ratio of advertising literature. This metric captures the idea of a piece of hardware pulling its own weight, i.e....
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Seattle, Wash.
1989
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| Series: | University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report
89,12,4 |
| Subjects: | |
| Summary: | We introduce a performance metric, normalized time, which is closely related to such measures as the area-time product of very large scale integration theory, and the price/performance ratio of advertising literature. This metric captures the idea of a piece of hardware pulling its own weight, i.e. contributing as much to performance as it costs in resources. We then prove general theorems for stating when the size of a given part is in balance with its utilization, and give specific formulas for commonly found linear and quadratic devices. We also apply these formulas to an analysis of a specific processor element, and discuss the implications for bit-serial vs word-parallel, RISC vs CISC, and VLIW designs. (kr). |
| Physical Description: | 16 S. |
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| 490 | 1 | |a University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report |v 89,12,4 | |
| 520 | 3 | |a We introduce a performance metric, normalized time, which is closely related to such measures as the area-time product of very large scale integration theory, and the price/performance ratio of advertising literature. This metric captures the idea of a piece of hardware pulling its own weight, i.e. contributing as much to performance as it costs in resources. We then prove general theorems for stating when the size of a given part is in balance with its utilization, and give specific formulas for commonly found linear and quadratic devices. We also apply these formulas to an analysis of a specific processor element, and discuss the implications for bit-serial vs word-parallel, RISC vs CISC, and VLIW designs. (kr). | |
| 650 | 4 | |a VLSI(Very Large Scale Integration) | |
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| 650 | 7 | |a Costs |2 dtict | |
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| 650 | 7 | |a Integrated circuits |2 dtict | |
| 650 | 7 | |a Operations Research |2 scgdst | |
| 650 | 7 | |a Processing equipment |2 dtict | |
| 650 | 7 | |a Quadratic equations |2 dtict | |
| 650 | 7 | |a Ratios |2 dtict | |
| 650 | 7 | |a Theorems |2 dtict | |
| 700 | 1 | |a Snyder, Larry |e Verfasser |4 aut | |
| 810 | 2 | |a Department of Computer Science: Technical report |t University of Washington <Seattle, Wash.> |v 89,12,4 |w (DE-604)BV008930431 |9 89,12,4 | |
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| id | DE-604.BV009260376 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:34:04Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006162252 |
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| physical | 16 S. |
| publishDate | 1989 |
| publishDateSearch | 1989 |
| publishDateSort | 1989 |
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| series2 | University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report |
| spelling | Ho, Samuel Verfasser aut Balance in architectural design Samuel Ho and Larry Snyder Seattle, Wash. 1989 16 S. txt rdacontent n rdamedia nc rdacarrier University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report 89,12,4 We introduce a performance metric, normalized time, which is closely related to such measures as the area-time product of very large scale integration theory, and the price/performance ratio of advertising literature. This metric captures the idea of a piece of hardware pulling its own weight, i.e. contributing as much to performance as it costs in resources. We then prove general theorems for stating when the size of a given part is in balance with its utilization, and give specific formulas for commonly found linear and quadratic devices. We also apply these formulas to an analysis of a specific processor element, and discuss the implications for bit-serial vs word-parallel, RISC vs CISC, and VLIW designs. (kr). VLSI(Very Large Scale Integration) Computer architecture dtict Costs dtict Electrical and Electronic Equipment scgdst Integrated circuits dtict Operations Research scgdst Processing equipment dtict Quadratic equations dtict Ratios dtict Theorems dtict Snyder, Larry Verfasser aut Department of Computer Science: Technical report University of Washington <Seattle, Wash.> 89,12,4 (DE-604)BV008930431 89,12,4 |
| spellingShingle | Ho, Samuel Snyder, Larry Balance in architectural design VLSI(Very Large Scale Integration) Computer architecture dtict Costs dtict Electrical and Electronic Equipment scgdst Integrated circuits dtict Operations Research scgdst Processing equipment dtict Quadratic equations dtict Ratios dtict Theorems dtict |
| title | Balance in architectural design |
| title_auth | Balance in architectural design |
| title_exact_search | Balance in architectural design |
| title_full | Balance in architectural design Samuel Ho and Larry Snyder |
| title_fullStr | Balance in architectural design Samuel Ho and Larry Snyder |
| title_full_unstemmed | Balance in architectural design Samuel Ho and Larry Snyder |
| title_short | Balance in architectural design |
| title_sort | balance in architectural design |
| topic | VLSI(Very Large Scale Integration) Computer architecture dtict Costs dtict Electrical and Electronic Equipment scgdst Integrated circuits dtict Operations Research scgdst Processing equipment dtict Quadratic equations dtict Ratios dtict Theorems dtict |
| topic_facet | VLSI(Very Large Scale Integration) Computer architecture Costs Electrical and Electronic Equipment Integrated circuits Operations Research Processing equipment Quadratic equations Ratios Theorems |
| volume_link | (DE-604)BV008930431 |
| work_keys_str_mv | AT hosamuel balanceinarchitecturaldesign AT snyderlarry balanceinarchitecturaldesign |