Proceedings of the IEEE 1989 Custom Integrated Circuits Conference: Town & Country Hotel, San Diego, Calif., May 15 - 18, 1989
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1989
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Internformat
MARC
LEADER | 00000nam a2200000 c 4500 | ||
---|---|---|---|
001 | BV009246082 | ||
003 | DE-604 | ||
005 | 00000000000000.0 | ||
007 | t | ||
008 | 940313s1989 |||| 10||| und d | ||
035 | |a (OCoLC)633018946 | ||
035 | |a (DE-599)BVBBV009246082 | ||
040 | |a DE-604 |b ger |e rakddb | ||
041 | |a und | ||
049 | |a DE-29T |a DE-83 | ||
111 | 2 | |a Custom Integrated Circuits Conference |n 11 |d 1989 |c San Diego, Calif. |j Verfasser |0 (DE-588)5043648-X |4 aut | |
245 | 1 | 0 | |a Proceedings of the IEEE 1989 Custom Integrated Circuits Conference |b Town & Country Hotel, San Diego, Calif., May 15 - 18, 1989 |
264 | 1 | |a San Diego, Calif. |c 1989 | |
300 | |a Getr. Zählung | ||
336 | |b txt |2 rdacontent | ||
337 | |b n |2 rdamedia | ||
338 | |b nc |2 rdacarrier | ||
650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 1989 |z San Diego Calif. |2 gnd-content | |
689 | 0 | 0 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
689 | 0 | |5 DE-604 | |
856 | 4 | 2 | |m HEBIS Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006152399&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
999 | |a oai:aleph.bib-bvb.de:BVB01-006152399 |
Datensatz im Suchindex
_version_ | 1804123693372145664 |
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adam_text | }
Proceedings of the
IEEE 1989
CUSTOM INTEGRATED CIRCUITS
CONFERENCE
Town amp; Country Hotel May 15-18, 1989
San Diego, California
Inv -Nr Z08H ß-os g
The CICC ‘89 is sponsored by the IEEE Electron Devices Society, the IEEE Solid-State Circuits
Council, and co-sponsored by the IEEE Rochester Section Its aim is to bring together designers,
producers and users of custom ICs to discuss recent developments and future directions in
custom integrated circuits
Fachbereichsbibliothek Informatik
TU Darmstadt
89CH2671-6
I
ONTENTS
ONDAY EVENING California Session 1
7:00 NEW PRODUCTS—NEW METHODS I
H Scalf, General Chairman
--------------♦---------------
ONDAY EVENING Golden West Session 2
7:00 NEW PRODUCTS—NEW METHODS II
A Silzars, General Chairman
-----------------♦-----------------
UESDAY MORNING Presidio Session 3 PAPER
8:00 WELCOME/OPENING REMARKS
R Milano, General Chairman
M Hartranft, Conference Chairman
8:20 CICC ‘89—Technical Program
D Brown, Technical Program Committee Chairman
8:30 KEYNOTE ADDRESS
“Design Automation for Analog and Mixed Analog/Digital ICs”
J Solomon
Co-Chairman of Cadence Design Systems, Inc
FLOORPLANNING AND ROUTING
Chairman: J Lipman
Co-Chairman: S Stevens
9:15 A Special Purpose Coprocessor Supporting Cell Placement and Floorplanning Algorithms 3 1
R-M Kling, P Banerjee, University of Illinois, Urbana, IL
9:40 A New Floorplanning Algorithm for Analog Circuits 3 2
C K Kim, E Berkcan, B Currin, M d’Abreu, General Electric Co , Schenectady, NY
10:05 A Hierarchical Floor-Planning, Placement, and Routing Tool for Sea-of-Gates Designs 3 3
C Ng, S Ashtaputre, E Chambers, K-H Do, S-T Hui, R Mody, D Wong, VLSI Technology, Inc , San Jose, CA
10:30 An Interior Point Method For Solving The Global Routing Problem 3 4
A Vannelli, University of Waterloo, Waterloo, Ont , Canada
10:55 A Gate Matrix Deformation and 3-Dimensional Maze Routing for Dense MOS Module Generation 3 5
Y Sone, S Suzuki, K Asada, University of Tokyo, Tokyo, Japan
11:20 An Efficient Layer Assignment Algorithm for Gridless Switchbox Routing 3 6
A Pitak, C Lursinsap, University of Southwestern Louisiana, Lafayette, LA
CONTENTS
TUESDAY MORNING Friars/Padre/Sierra Session 4 P
ANALOG AND DIGITAL DESIGN SYNTHESIS
Chairman: M Mittal
Co-Chairman: R Bryant
9:15 LOGOPT—A Multi-Level Logic Synthesis and Optimization System A M Prabhu, AT amp;T Bell Labs Murray Hill, NJ 4
9:40 CHARM: A Synthesis Tool for High-Level Chip-Architecture Planning K-H Temme, University of Dortmund, Dortmund, W Germany 4
10:05 ACACIA: The CMU Analog Design System L R Carley, D Garrod, R Harjani, J Kelly, T Lim, E Ochotta, R A Rutenbar, Carnegie Mellon University, Pittsburgh, PA 4
10:30 From Analog Design Description to Layout: A New Approach to Analog Sililcon Compilation E Berkcan, C K Kim, B Currin, M d’ Abreu, General Electric Co , Schenectady, NY 4
10:55 An Integrated Switched Capacitor Filter Design System A Barlow, K Takasuka, Y Nambu, T Adachi, J Konno, Asahi Kasei Microsystems, Tokyo, Japan 4
11:20 LATE NEWS PAPER Design Automation System for Analog Circuits Based on Fuzzy Logic 4
M Hashizume, H Y Kawai, K Nii, T Tamesada, University of Tokushima, Tokushima-shi, Japan
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TUESDAY MORNING Golden West Session 5 P
PROGRAMMABLE DEVICES Chairman: G Ledenbach Co-Chairman: S Chiao
9:15 A 6 Nanosecond CMOS EPLD With uW Standby Power M J Allen, Intel Corp , Folsom, CA 5
9:40 A Function Specific EPLD for the PS/2 Micro Channel Bus Adapter Y-F Chan, C-Y Hung, C Hsiao, P Wong, N Lee, C McClintock, Altera Corp , Santa Clara, CA 5
10:05 The Effect of Logic Block Complexity on Area of Programmable Gate Arrays J Rose*, R J Francis**, P Chow**, D Lewis**, Stanford University, Stanford, CA*; University of Toronto, Toronto, Ont , Canada** 5
10:30 Electrical and Geometrical Circuit Performance Using an Advanced Sea-of-Gates Philosophy P Duchene*, H Heeb**, A Osseiran*, M Declercq*, W Fichtner**, Swiss Federal Institute of Technology, Lausanne, Switzerland*, Swiss Federal Institute of Technology, Zurich, Switzerland** 5
10:55 A12ns, CMOS Programmable Logic Device for Combinatorial Applications S P Gowni*, P E Platt*, A L Hawkins*, W R Hiltpold*, S M Douglass**, Cypress Semiconductor Corp , Starkville, MS*; Cypress Semiconductor Corp , San Jose, CA** 5
11:20 A75 ns 350mW BiCMOS PAL®-type Device R Leung, K Le, C Sung, Y-M Chu, G Conner, R Lane, J L deJong, SigneticsCo , Sunnyvale, CA 5
11:45 LATE NEWS PAPER
A15ns 2500 Gate Highly Flexible CHMOS EPLD R W Swartz, M J Allen, Intel Corp , Folsom, CA 5
12:00 LATE NEWS PAPER
A 5000-Gate CMOS EPLD With Multiple Logic and Interconnect Arrays S C Wong, H C So, J H Ou, J Costello, Altera Corp , Santa Clara, CA 4 5
CONTENTS
TUESDAY MORNING California Session 6 PAPER
DATA CONVERTERS Chairman: J Tandon Co-Chairman: L D’Luna
9:15 A16-Bit 160 kHz CMOS A/D Converter Using Sigma-Delta Modulation M Rebeschini*, N van Bavel**, P Rakers*, R Greene*, J Caldwell*, J Haug*, Motorola Corp Res Design Labs, Schaumburg, IL*; Motorola Telecom Design, Austin, TX** 6 1
9:40 Anil Bit, 50 kSample/s CMOS A/D Converter Cell Using a Multislope Integration Technique J-G Chern, A A Abidi, University of California, Los Angeles, CA 6 2
10:05 An 8-Bit Two-Step Flash A/D Converter for Video Applications A Cremonesi*, F Maloberti**, G Torelli**, C Vacchi**, ST Microelectronics Agrate Brianza, Milano, Italy*; University Pavia, Pavia, Italy** 6 3
10:30 A12Bit 5 jusec CMOS Recursive ADC with 25mW Power Consumption M Yotsuyanagi, A Yukawa, K Hino-oka, K Shiraki, H Abiko, NEC Corp , Kanagawa, Japan 6 4
10:55 CMOS Low Distortion Sample amp; Hold Circuit for Audio D/A Converter N Sugawa, T Ikarashi, K Kuwana, T Kawakami, A Kimitsuka, T lida, Toshiba Microelectronics Corp , Kawasaki, Japan 6 5
11:20 A Complete Single Supply CMOS 12 Bit DAC S Hisano, M P Timko, Analog Devices, Wilmington, MA 6 6
11:45 LATE NEWS PAPER
A10-Bit High Speed CMOS DAC Macrocell A W Vogt, I J Dedic, Advanced Microelectronic Systems, Wembley, UK67
TUESDAY AFTERNOON Presidio Session 7 PAPER
MIXED ANALOG/DIGITAL APPLICATIONS 1 Chairman: D A Wayne Co-Chairman: A Grebene
1:30 A 30 MHz Low-Noise CMOS Preamplifier for Disk Drive Heads T-W Pan, A A Abidi, University of California, Los Angeles, CA 7 1
1:55 A Differential PLL Architecture for High Speed Data Recovery R S Co ,JC Liang, K W Ouyang, Western Digital Corp , Irvine, CA 7 2
2:20 A High-Performance Perpendicular FDC Using Analog and Digital Standard Cell Methodology K Matsuo*, S Fujii*, K Kasai**, 1 Tsuchiya**, T Sasaki*, K Toda*, T Yoshizuka*, K Suzuki*, M Kamata*, M Kaizuka*, Toshiba Corp , Kawasaki, Japan*; Toshiba Microcomputer Eng Corp , Kawasaki, Japan** 7 3
2:45 CMOS Analog Front-End for Conversational Video Phone Modem C W Solomon*, L Ozcolak*, G Sellani*, W E Brisco**, EXAR Corp , San Jose, CA*; Luma Telecom, Inc , Sunnyvale, CA** 7 4
3:10 A Precision Optical Metering System for Medical Instrumentation W R Krenik*, D Gonzalez*, E G Dierschke*, L J Izzi*, B Carter*, J White**, R Miller**, Texas Instruments Inc , Dallas, TX*; Miles, Inc , Mishawaka, IN** 7 5
3:35 A Four Chip Implantable Defibrillator/Pacemaker Chipset J G Ryan, K J Carroll, B D Pless, Ventritex, Inc , Sunnyvale, CA 7 6
4:00 A Novel BiMOS Switch for Use in Switched-Capacitor Filters 1 Abu-Khater, E l El-Masry, Technical University of Nova Scotia, Halifax, NS, Canada 7 7
CONTENTS
TUESDAY ARTERNOON
Friars/Padre/Sierra Session 8 PAPER
HIGH DENSITY/PERFORMANCE GATE ARRAYS
Chairman: R Blake
Co-Chairman: G Sporzynski
1:30 AI 77K Gate 150 PS CMOS SOG with 1856 I/O Buffers
M Murayama, Y Matsuda, K Yoshida, H Ooka, T Otani, S Toyoda, F Tsubokura, A Aso, NEC Corp ,
Kanagawa, Japan
1:55 08Mm1 4M Tr CMOS SOG Based on Column Macro-Cell
Y Okuno, M Okabe, T Arakawa, I Tomioka, T Ohno, T Noda, Y Kuramitsu, Mitsubishi Electric Corp , Hyogo,
Japan
2:20 BiNMOS: A Basic Cell for BiCMOS Sea-of-Gates
A El Gamal, J L Kouloheris, D How, M Morf, Stanford University, Stanford, CA
2:45 A 270 ps/24 000 Gate BiCMOS Gate Array
A Denda, K Yamada, T Hatano, H Okamura, N Aoki, M Iruka, N Kusunose, H Ogawa, S Saigo, NEC Corp ,
Kawasaki, Japan
3:10 A 350 ps 50K 08mm BiCMOS Gate Array With Shared Bipolar Cell Structure
H Hara, Y Sugimoto, M Noda, T Nagamatsu, Y Watanabe, H Iwai, Y Niitsu, G Sasaki, K Maeguchi, Toshiba
Corp , Kawasaki, Japan
3:35 A100K Gate Sub-Micron BiCMOS Gate Array
J Gallia, A Yee, l-F Wang, K Chau, H Davis, S Swamy, T Sridhar, V Nguyen, K Ruparel, K Moore,
C Lemonds, B Chae, P Eyres, T Yoshino, J Pozadzides, R Fine, A Shah, Texas Instruments, Dallas, TX
4:00 A05mm BiCMOS Channelless Gate Array
F Murabayashi*, Y Nishio*, H Maejima*, A Watanabe*, S Shukuri**, T Nishida**, K Shimohigashi**, Hitachi
Research Lab, Ibaraki-ken, Japan*; Hitachi Central Research Lab, Tokyo, Japan**
8 1
8 2
8 3
8 4
8 5
8 6
8 7
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TUESDAY AFTERNOON Golden West Session 9 PAPER
DEVICE MODELING
Chairman: R Milano
Co-Chairman: H Scalf
1:30 Physics-Based Bipolar Transistor Model for Low-Temperature Circuit Simulation 9 1
J J Liou*, J S Yuan**, University of Central Florida, Orlando, FL*; University of Florida, Gainesville, FL**
1:55 Steady-State Bipolar Transistor Simulator for the 77° K—300° K Temperature Range 9 2
M Chrzanowska-Jeske, R C Jaeger, Auburn University, Auburn, AL
2:20 A Simplified Approach for Quasi-Three-Dimensional Modeling npn Transistors 9 3
P M Zeitzoff, AT amp;T Bell Labs, Allentown, PA
2:45 A Technology-Independent Device Modeling Program Using Simulated Annealing Optimization 9 4
M-K Vai, MFD Ng, Northeastern University, Boston, MA
3:10 An Improved l-V Model of Small Geometry MOSFETs for SPICE 9 5
S C Chung, T S Lin, Y G Chen, National Chiao Tung University, Taiwan, R O C
3:35 A Three-Transistor Model for Submicron MOSFET 9 6
S C Wong, H C Lin, University of Maryland, College Park, MD
4:00 Simulating the Effects of Single-Event and Radiation Phenomena on GaAs MESFET Integrated 9 7
Circuits
P George, P-K Ko, C Hu, University of California, Berkeley, CA
ONTENTS
UESDAY AFTERNOON California Session 10 PAPER
COMPUTER ELEMENTS
Chairman: A Goodman
Co-Chairman: M Horowitz
1:30 A High Density NAND EEPROM with Block-Page Programming for Microcomputer Applications 10 1
M Momodomi, Y Iwata, T Tanaka, Y Itoh, R Shirota, F Masuoka, Toshiba Corp , Kawasaki, Japan
1:55 A 2Kbyte Fully-Associative Cache Memory With On-Chip DRAM Control 10 2
S Golson*, S Griffith**, Trilobyte Systems, Carlisle, MA*; Sun Microsystems, Billerica, MA**
2:20 A15 ns 32 x 32-Bit CMOS Multiplier With an Improved Parallel Structure 10 3
M Nagamatsu, S Tanaka, J Mori, T Noguchi, K Hatanaka, Toshiba Corp , Kawasaki, Japan
2:45 A 3 8ns CMOS 16x16 Multiplier Using Complimentary Pass Transistor Logic 10 4
K Yano, T Yamanaka, T Nishida, M Saitoh, K Shimohigashi, A Shimizu, Hitachi Central Research Lab, Tokyo,
Japan
3:10 A Custom Processor for Use in a Parallel Computer System 10 5
D K Wilde, NCUBE Corp , Beaverton, OR
3:35 A140Mb/s CMOS Crosspoint Chip for Switching Networks With Dynamic Path-Rearrangement 10 6
K G Hess*, G Kettler**, W Schmidt**, Fraunhofer Institute of Microelectronic Circuits amp; Systems, Duisburg, W
Germany*, Forschungsinstitut der Deut Bunde, beim Fernmelde Zent , Darmstadt, W Germany**
4:00 An ECL Compatible Full CMOS 210Mbps Crosspoint Switch 10 7
T Yoneda, M Komaki, S Sugatani, Y Ezaki, Fujitsu VLSI Ltd , Aichi, Japan
4:25 LATE NEWS PAPER
A BiCMOS 32-Bit Execution Unit for 70MHz VLSI Computer 10 8
S Tanaka*, T Hotta*, M Iwamura*, T Yamauchi*, T Bandoh*, A Hotta**, T Nakano**, S Iwamoto***,
S Adachi***, Hitachi, Ibaraki-ken, Japan*, Hitachi, Tokyo, Japan**, Hitachi, Aichi-ken, Japan***
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EDNESDAY MORNING Regency Hall Session 11 PAPER
MIXED ANALOG/DIGITAL APPLICATIONS II
Chairman: J Buurma
Co-Chairman: K Au
8:30 CMOS High Speed Digital Datastrobe Processor 11 1
T Komatsu*, K Watanabe*, E Minamimura*, Y Kowase*, S Ueda*, N Hohe*, S Asai**, T Matsuura**, Hitachi
Ltd , Gunman, Japan*; Hitachi Ltd , Tokyo, Japan**
8:55 Design of an Analog 8-Bit 2 Channel I/O ASIC for Disk Drive Control Applications 11 2
P Quinlan, Analog Devices, BV, Limerick, Ireland
9:20 A16 MBPS Adapter Chipfor the IBM Token-Ring Local Area Network 11 3
J D Blair, A Correale, Jr ,HC Cranford, D A Dombrowski, C K Erdelyi, C R Hoffman, J L Lamphere, K W
Lang, J K Lee, J M Mullen, V R Norman, S F Oakland, IBM Corp , Research Triangle Park, NC
9:45 An Intelligent Multiplexer/Driver Integrated Circuit for an Implantable Multichannel Blood 11 4
Flowmeter
K-W W Yeung, J D Meindl, Stanford University, Stanford, CA
10:10 A CMOS Camera ControllC 11 5
I Muenster*, B J Hosticka*, T Neumann*, G Zimmer*, W Bletz**, R Magel**, Fraunhofer Inst, of Microelectronic
Circuits amp; Systems, Duisburg, W Germany*; Leica GmbH, Solms bei Wetzlar, W Germany**
10:35 An Integrated Digital Y/C Separator for S-VHS VCR’s 11 6
H Owashi*, K Minabe*, H Otsubo*, T Kuroyanagi*, S Ueda**, H Torii***, Hitachi Cons Prod Res Ctr ,
Yokohama, Japan*; Hitachi Takasaki Works**; Hitachi Tokai Works***
11:00 LATE NEWS PAPER
A CMOS 100MHz Digital Oscilloscope Point Processor and Time Base Integrated Circuit 11 7
E Etheridge, Tektronix, Inc , Beaverton, OR
WEDNESDAY MORNING Friars/Padre/Sierra Session 12 PAPER
HIGHLY PARALLEL ARCHITECTURES AND NEURAL NETS
Chairman: P Ivey Co-Chairman: D Brown
8:30 BLITZEN: A VLSI Array Processing Chip R A Heaton, D W Blevins, Microelectronics Center of North Carolina, Research Triangle Park, NC 12 1
8:55 A Four-Processor Building Block for SIMO Processor Arrays A L Fisher, P T Highnam, T E Rockoff, Carnegie Mellon University, Pittsburgh, PA 12 2
9:20 A High Speed Data Encryption Processor for Public Key Cryptography T Rosati, Calmos Systems, Inc , Kanata, Ont , Canada 12 3
9:45 A VLSI Fuzzy Logic Inference Engine for Real-Time Process Control W D Dettloff*, K E Yount*, H Watanabe**, Microelectronics Center of North Carolina, Research Triangle Park, NC*; University of North Carolina, Chapel Hill, NC** 12 4
10:10 A Bit-Serial VLSI Receptive Field Accumulator 12 5
K Strohbehn*, A G Andreou**, The Johns Hopkins University, Laurel, MD*; The Johns Hopkins University, Baltimore, MD**
10:35 A Synthetic Neural Integrated Circuit L A Akers, M Walker, R Grondin, D Ferry, Arizona State University, Tempe, AZ 12 6
11:00 Fully Digital Neural Network Implementation Based on Pulse Density Modulation J Tomberg, T Ritoniemi, K Kaski, H Tenhunen, Tampere University of Technology, Tampere, Finland 12 7
9 WEDNESDAY MORNING Golden West Session 13 PAPER
SIMULATION! Chairman: V B Rao Co-Chairman: D Johnson
8:30 iSPLICE3: A New Simulator for Mixed Analog/Digital VLSI Circuits E Acuna, J Dervenis, A Pagones, R Saleh, University of Illinois, Urbana, IL 13 1
8:55 A New Multi-Level Timing Simulation Environment for Timing Verification J Benkoski, M Chew, A Strojwas, Carnegie Mellon University, Pittsburg, PA 13 2
9:20 Hierarchical Timing View Generation Including Accurate Modeling for False Paths P Das*, P Johannes*, L Claesen*, H DeMan**, IMEC, Leuven, Belgium*; Kath University of Leuven, Leuven, Belgium** 13 3
9:45 An Analytical Model for BiCMOS Logic Transient Resopnse Allowing Parameter Variations P L Heedley, R C Jaeger, Auburn University, AL 13 4
10:10 Analysis of Pulse Propagation on High-Speed VLSI Chips M Nakhla, Carleton Universtiy, Ottawa, Ont , Canada 13 5
10:35 An Approach to Understanding Evaluation of Simulation Results as an Integrated Task R Buschke, K Lagemann, University Hamburg, Hamburg, W Germany 13 6
CONTENTS
WEDNESDAY MORNING
California Session 14 PAPER
PACKAGING AND INTERFACES
Chairman: W A Vincent
Co-Chairman: M G Moon
8:30 Single Package 32Bit Floating Point Digital Signal Processor with Built-In 64K Byte SRAM Cache 14 1
J M Segelken, AT amp;T Bell Labs, Murray Hill, NJ
8:55 Packaging Structures Utilizing New “Pinless” Grid Array Technologies and Vacuum Well 14 2
Processes to Provide Enhanced Reliability and Circuit Densities
P Nunally, General Dynamics Corp , Pomona, CA
9:20 VLSI Performance Compensation for Off-Chip Drivers and Clock Generation 14 3
D T Cox*, D L Guertin*, C L Johnson*, R A Piro**, B G Rudolph*, D W Stout**, R R Williams*, IBM Application
Business, Systems Div , Rochester, MN*; IBM Corp , Essex Junction, VT**
9:45 Low dl/dt Noise and Reflection Free CMOS Signal Driver 14 4
M Hashimoto, O-K Kwon, Texas Instruments Inc , Dallas, TX
10:10 A Monolithic 50—200 MHz CMOS Clock Recovery and Retiming Circuit 14 5
R J Baumert, P C Metz, M E Pedersen, R L Pritchett, J A Young, AT amp;T Bell Labs, Allentown, PA
10:35 High Voltage CMOS LCD Driver Using Low Voltage CMOS Process 14 6
J Haas*, K Au*, L Martin*, T L Portlock*, T Sakurai**, Motorola, Inc , Austin, TX*; Motorola Nippon Ltd , Tokyo,
Japan**
11:00 4 0Gb/s NMOS Laser Driver 14 7
K R Shastri, K A Yanushefski, J L Hokanson, M J Yanushefski, AT amp;T Bell Labs, Allentown, PA
11:25 LATE NEWS PAPER
4Gb/s ECL Gate Masterslice 14 8
M Tamamura, S Emori, Y Watanabe, I Shimotuhama, N Kikuchi, W Ishibashi, K Tachibana, Fujitsu Ltd ,
Kawasaki, Japan __________________^____________________
WEDNESDAY AFTERNOON Regency______________________Session 15____________PAPER
DIGITAL ASICs
Chairman: D Perkins
Co-Chairman: D Daly ~
2:00 Design of a Digital Audio Input Output Chip 15 1
M M Ligthart*, A Bechtolsheim**, G DeMicheli***, A El Gamal***, Philips Research Lab , Sunnyvale, CA*;
Sun Microsystems, Mountain View, CA**; Stanford University, Stanford, CA***
2:25 VLSI Architecture for IEEE802 5 Token-Ring LAN Controller 15 2
K Tanaka*, K Fujimoto*, E Katsumata*, T Yaguchi*, K Tamaru*, A Kanuma*, S lida**, A Nishikawa**,
H Shiraishi**, T Mineoka***, T Shimamura***, Toshiba Semiconductor Device Eng Lab , Kawasaki, Japan*;
Toshiba Semiconductor System Eng Center, Kawasaki, Japan**; Toshiba Microcomputer Engineering Co ,
Kawasaki, Japan***
2:50 Mixed Design Approaches on the Semicustom CMOS Gate Forest 15 3
J Kernhof, M Schau, M Beunder, W Haas, B Hoefflinger, Institute for Microelectronics, Stuttgart, W Germany
3:15 High Performance Clock Distribution for CMOS ASICs 15 4
S Boon*, S Butler*, R Byrne*, B Setering*, M Casalanda**, A Scherf**, VTC Incorporated, Bloomington, MN*;
Control Data Corp , Bloomington, IN**
3:40 Q20D080 Analog RAM Logic Array 15 5
C Blake, M Hollabaugh, Applied Micro Circuits Corp , San Diego, CA
4:05 0 6 Aim 12K-Gate ECL Gate Array With RAM and ROM 15 6
T Nishimura, H Satoh, M Tatsuki, A Ohba, S Hine, K Uga, Y Kuramitsu, Mitsubishi Electric Corp , Hyogo, Japan
4:30 13000 Gate ECL Compatible GaAs Gate Array 15 7
W Larkins, S Canaga, G Lee, W Terrell, I Deyhimy, Vitesse Semiconductor Corp , Camarillo, CA
4:55 LATE NEWS PAPER
A1 4ns/64kb RAM with 85ps/3680 Logic Gate Array 15 8
M Kimoto, H Shimizu, Y Ito, K Kohno, M lkeda, T Deguchi, N Fukuda, K Ueda, S Harada, K Kubota, Fujitsu
Ltd , Kawasaki, Japan
CONTENTS
WEDNESDAY AFTERNOON Friars/Padre/Sierra Session 16 PAPER
TELECOMMUNICATION CIRCUITS
Chairman: C Jungo
Co-Chairman: D M Embree
2:00 An Analog Front End Chip for V 32 Modems 16 1
J P Roesgen*, G H Warren**, Concord Data Systems, Marlborough, MA*; IMP, San Jose, CA**
2:25 An Analog Front End for High Speed Fast Turnaround Modems 16 2
R Y Halim, D Shamlou, J Illgner, Hayes Microcomputer Products, Inc , Norcross, GA
2:50 A^O^AnahMFront Ei^dfty-High Speed Modems 16 3
eff* J^^^^y^^^^t^yst*, J Barner*, J Plary*, T El-Kiki**, D McGuire**, AT amp;T Bell Labs, Murray
3:15 Analog Front-End of an ECBM Transceiver for ISDN 16 4
R Castello*, L Tomasini**, S Pernici**, F Salerno***, M Mazzucco***, M Ferro***, University of Pavia, Pavia,
Italy*; SGS-Thomson Microelectronics, Agrate Brianza, Italy**; CSELT, Torino, Italy***
3:40 A Single Chip S-Interface Transceiver for Public and Private ISDN 16 5
F Van Simaeys, J Adams, D Rabaey, M Rahier, Alcatel—Bell Telephone Mfg Cy, Antwerp, Belgium
4:05 A Codec with On-Chip Digital Echo Canceller 16 6
V Friedman*, J M Khoury*, L J Loporcaro*, M J Theobald*, E M Fields*, M F Tompsett*, V P Gopal**, G L
Lustro**, M Figueroa**, AT amp;T Bell Labs, Murray Hill, NJ*; AT amp;T Bell Labs, Naperville, IL**
4:30 A No-Trimming SLIC Two-Chip Set With Coin Telephone Signaling Facilities 16 7
M Akata, Y Nagataki, K Koyabu, K Mukai, S Yoshida, I Ueki, NEC Corp , Kawasaki, Japan
4:55 LATE NEWS PAPER
A 400MHz CMOS Packet Transmitter-Receiver Chip 16 8
A J-H Lee, J A Sabnis, M W Saniski, G P Sampson, III, AT amp;T Bell Labs Allentown, PA
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WEDNESDAY AFTERNOON Golden West Session 17 PAPER
PERFORMANCE OPTIMIZATION
Chairman: M Tarsi
Co-Chairman: J Barnes
2:00 Automatic Circuit and Layout Design for Mixed Analog/Digital ASICs 17 1
J Trontelj, L Trontelj, T Slivnik, T PleterSek, G Shenton, IMP Europe Ltd , Wilts, U K
2:25 PROMPT3—A Cell-Based Transistor Sizing Program Using Heuristic and Simulated Annealing 17 2
Algorithms
M-C Chang, C-F Chen, AT amp;T Bell Labs, Murray Hill, NJ
2:50 MOSIZ: A Two-Step Transistor Sizing Algorithm Based on Optimal Timing Assignment Method 17 3
of Multi-State Complex Gates
Z-J Dai, K Asada, University of Tokyo, Tokyo, Japan
3:15 Operational Amplifier Compilation with Performance Optimization 17 4
H Onodera, H Kanbara, K Tamaru, Kyoto University, Kyoto, Japan
3:40 Optimal Ordering of Gate Signals in CMOS Complex Gates 17 5
M Lefebvre*, C Chan**, Bell-Northern Research, Ottawa, Ont , Canada*; Carleton University, Ottawa, Ont ,
Canada**
4:05 Geometric Compaction of Building-Block Layout 17 6
X-M Xiong, E S Kuh, University of California, Berkley, CA
4:30 SDC Cell—A Novel CMOS/BiCMOS Design Methodology for Mainframe Arithmetic Module 17 7
Generation
T Hayashi*, T Doi*, M Asai*, K Ishibashi*, S Shukuri*, A Watanabe**, M Suzuki*, Hitachi Central Research Lab,
Tokyo, Japan*; Hitachi Research Lab, Ibaraki, Japan**
1
CONTENTS______________________________________________________________
EDNESDAY AFTERNOON California Session 18 PAPER
FABRICATION TECHNOLOGY Chairman: M Hartranft Co-Chairman: P Zeitzoff
1:50 TUTORIAL
Applications of CVD Tungsten in VLSI Circuits S Mehta, Cypress Semiconductor, San Jose, CA 18 1
2:25 A Submicron CMOS Triple Level Metal Technology for ASIC Applications D Fisher, K Y Chang, F Pintchovsky, J Klein, K-Y Fu, S Lai, R Dillard, Motorola, Inc , Austin, TX 18 2
2:50 GaAs MESFET Digital Integrated Circuits Fabricated with Low Temperature Buffer Technology M J Delaney, C S Chou, L E Larson, J F Jensen, D S Deakin, A S Brown, W W Hooper, M A Thompson, L G McCray, S E Rosenbaum, Hughes Research Labs, Malibu, CA 18 3
3:15 A 5-Volt Only Flash EEPROM Technology for High Density Memory and System 1C Applications M Gill, R Cleavelin, S Lin, 1 D’Arrigo, G Santin, P Shah, A Nguyen, R Lahiry, P DeSimone, G Piva, J Paterson, Texas Instruments Inc , Houston, TX 18 4
3:40 A Submicron Analog CMOS Technology R W Gregor*, K J O’Brien*, G R Wesley*, W H Stinebaugh, Jr **, H Chew*, C W Leung*, AT amp;T Bell Labs, Allentown, PA*; AT amp;T Bell Labs, Murray Hill, NJ** 18 5
4:05 A BiCMOS Technology with 660MHz Vertical PNP Transistor for Analog/Digital ASICs K Soejima, A Shida, M Hirata, H Koga, J Ukai, H Sata, NEC Corp , Kanagawa, Japan 18 6
4:30 A Dual-Poly (n + /p +) Gate, Ti-Salicide, Double-Metal Technology for Submicron CMOS ASIC and Logic Applications S W Sun, M Swenson, J R Yeargain, C-O Lee, C Swift, J R Pfiester, W Bibeau, W Atwell, Motorola, Inc , Austin, TX 18 7
-----------------♦------------
EDNESDAY EVENING PANEL Friars/Padre/Sierra
8:00 SILICON COMPILATION ON TRIAL: YOU BE THE JURY
Moderator: J Lipman
VLSI Technology
----------------♦---------
EDNESDAY EVENING PANEL Golden West
8:00 MIXED MODE ASIC IN THE 90S: STILL WED TO CUSTOM
Moderator: H L Scalf
American Microsystems, Inc
-----------------♦------------------
EDNESDAY EVENING PANEL California
8:00 WHAT IS THE ROLE OF UNIVERSITIES IN THE 1C DESIGN BUSINESS?
Moderator: R Saleh
University of Illinois
CONTENTS
THURSDAY MORNING Regency Session 19 PAPE
CAD SYSTEMS FOR DESIGNS AND SPECIFICATIONS
Chairman: A Barlow
Co-Chairman: T Sideris
8:30 The Input/Output Specifications Analyzer for 1C Designs E S Lee, H T Chang, R Kovesdi, K W Su, AT amp;T Bell Labs, Murray Hill, NJ 19 1
8:55 An Approach to Knowledge-Based ASIC-Specification K D Mueller-Glaser, J Bortolazzi, University of Erlangen, Neurnberg, W Germany 19 2
9:20 Design Methodologies and CAD Tools C Piguet, CSEM, Neuchatel, Switzerland 19 3
9:45 An Advanced Design System: Design Capture, Functional Test Generation, Mixed Level Simulation and Logic Synthesis M Sekine*, T Takei*, M Aihara*, E Yano*, K Yamagishi*, K Kohno*, K Kitahara*, T Fukasawa*, K Iwawaki*, S Ueda**, M Kogure**, Toshiba ULSI Research Center, Kawasaki, Japan*; Toshiba Ome Works, Ome City, Japan** 19 4
10:10 Optimized Design Method for Full-Custom Microprocessors K Usami, J Iwamura, Toshiba Corp , Kawasaki, Japan 19 5
10:35 A Fully Integrated Design Methodology For 100K-Gate CMOS Custom LSIs With TAB Packaging T Yamamura, K Kuwano, S Sugatani, T Tsujimura, Fujitsu Ltd , Kawasaki, Japan 19 6
11:00 Computer Aids for High Performance CMOS Custom Design T C Poon, Y T Oh, W A Oswald, P Magarshack, AT amp;T Bell Labs, Allentown, PA a 19 7
THURSDAY MORNING Friars/Padre/Sierra Session 20 PAPE
DIGITAL PROCESSORS AND SPEECH RECOGNITION
Chairman: S Hao
Co-Chairman: L Christopher
8:30 A Mask Programmable DSP Array R D Albon, G E Floyd, J E Coles, Plessey Semiconductors Ltd , Plymouth, U K 20 1
8:55 A High-Speed FIR Filter Designed by Compiler R Hartley, P Corbett, P Jacob, S Karr, General Electric Co , Schenectady, NY 20 2
9:20 A 20-Bit Decimator 1C for High-Resolutioin Audio A/D Conversion R W Adams*, J Frenkil**, D Gottfried**, P Pinelle**, dbx Inc , Newton, MA*; VLSI Technology, Inc , Wilmington, MA** 20 3
9:45 The Design of DSP Components for the CD Digital Audio System Using Silicon Compilation Techniques R Woudsma, A Delaruelle, Philips Res Labs, Eindhoven, The Netherlands 20 4
10:10 A Multi-Channel Digital Demodulator for LVDT and RVDT Position Sensors F F Yassa*, S L Garverick*, G Ngo**, R Hartley*, J Prince**, J Lam**, S Noujaim*, R Korsunsky**, J Thomas*, G E Co , Schenectady, NY*; G E Co , Binghamton, NY** 20 5
10:35 RIPAC: A VLSI Processor for Speech Recognition L Licciardi*, M Paolini*, R Tasso*, A Torielli*, R Cecinati**, CSELT, Torino, Italy*; Elettronica San Giorgio, Genova, Italy** 20 6
11:00 A VLSI Wordprocessing Subsystem for a Real Time Large Vocabulary Continuous Speech Recognition System A Stolzle, S Narayanaswamy, K Kornegay, J Rabaey, R W Brodersen, University of California, Berkeley, CA 20 7
i
CONTENTS
HURSDAY MORNING Golden West Session 21 SIMULATION II Chairman: R Saleh Co-Chairman: D Johnson PAPER
8:30 Switched-Capacitor Simulation Models for Full-Chip Verification T Chanak*, R Chadha**, K Singhal***, Stanford University, Stanford, CA*; AT amp;T Bell Labs, Murray Hill, NJ**; AT amp;T Bell Labs, Allentown, PA*** 21 1
8:55 Functional-Level Simulation of Switched-Capacitor Circuits with Non-Ideal Switches and Operational Amplifiers D Giannopoulos, S Wong, A Lish, Philips Labs, Briarcliff Manor, NY 21 2
9:20 9:45 Dominant Pole(s)/Zero(s) Analysis for Analog Circuit Design L T Pillage, C M Wolff, R A Rohrer, Carnegie Mellon University, Pittsburgh, PA Extending SPICE for Electro-Thermal Simulation R S Vogelsong, C Brzezinski, University of South Florida, Tampa, FL 21 3
10:10 Computing DC Large Change Sensitivities D Divekar, H Daseking, R Apte, Valid Logic Systems, San Jose, CA 21 5
10:35 Statistical Sensitivity Analysis of MOSFET Integrated Circuits Using Process Database W S Wong*, R S Winton*, J J Liou**, Mississippi State University, Mississippi State, MS*; University of Central Florida, Orlando, FL** 21 6
11:00 A Fast Multipole Algorithm for Capacitance Extraction of Complex 3-D Geometries K Nabors, J White, MIT, Cambridge, MA 4 21 7
HURSDAY MORNING California Session 22 PAPER
TEST
Chairman: P Fasang
Co-Chairman: S Davidson
8:30 A Self-Testing ALU Using Built-In Current Sensing 22 1
P Nigh, W Maly, Carnegie Mellon University, Pittsburgh, PA
8:55 A Serial Interfacing Technique for Built-In and External Testing of Embedded Memories 22 2
B Nadeau-Dostie*, A Silburt*, V K Agarwal**, Bell-Northern Research Ltd , Ottawa, Canada*; McGill University,
Montreal, Canada**
9:20 Detecting Stuck-Open Faults With Stuck-At Test Sets 22 3
S D Millman, E J McCtuskey, Stanford University, Stanford, CA
9:45 Boundary Scan amp; Its Application to Analog-Digital ASIC Testing in a Board/System Environment 22 4
P P Fasang, National Semiconductor Corp , Santa Clara, CA
10:10 Practical Built-In Test of CMOS State Machines with Realistic Faults: A System Perspective 22 5
M Katoozi*, M Soma**, Seattle Silicon Corp , Bellevue, WA*; University of Washington, Seattle, WA**
10:35 Physical Design of Testable VLSI: Techniques and Experiments 22 6
M Levitt*, J Abraham**, University of Illinois, Urbana, IL*; University of Texas, Austin, TX**
11:00 LATE NEWS PAPER
Testing and Failure Analysis Methodology of the NS32532 Microprocessor 22 7
E Shihadeh, M Beck, D Biran, Y Hoffman, T Uran, B Maytal, Y Milkstein, R Nasrallah, Y Nero, National
Semiconductor (I C ) Ltd , Migdal Haemek, Israel
CONTENTS
THURSDAY AFTERNOON Regency Session 23 PAPE
COMPLEX MODULE GENERATION AND ASSEMBLY
Chairman: J Barnes
Co-Chairman: H-F S Law
1:00 A Compiler for Optimized Arithmetic Datapaths 23 1
K F Pang, H J Huang, LSI LogicCorp , Menlo Park, CA
1:25 A Datapath Multiplier with Automatic Insertion of Pipeline Stages 23 2
C Asato, C Ditzen, S Dholakia, VLSI Technology, Inc , San Jose, CA
1:50 An N-Bus Datapath Compiler for 1C Design 23 3
R Gordon, S McNeary, T Ng, Y Rotblum, M Tate, Silicon Compiler Systems Corp
2:15 Al Ojum Compilable FIFO Buffer for Standard Cell 23 4
M Kawauchi*, M Haraguchi*, Y Okada*, Y Tanaka**, H Suzuki**, Toshiba Microelectronics Corp , Kawasaki,
Japan*; Toshiba Corp , Kawasaki, Japan**
2:40 A Generator for High-Density Macrocells With Hierarchical Structure 23 5
K Takeya, M Nagatani, S Horiguchi, NTT LSI Laboratories, Atsugi, Japan
3:05 High Speed Multi-Port Static RAM Silicon Compiler 23 6
H H Hana, S J Hussain, Seattle Silicon Corp , Bellevue, WA
3:30 PANDA—A Hierarchical Mixed Mode VLSI Module Assembler 23 7
W R Bulllman, L A Davieau, H S Moscovitz, G D O’Donnell, AT amp;T Bell Labs, Allentown, PA
3:55 LATE NEWS PAPER
Modular Design of a High Performance 32-bit Microcontroller 23 8
R Skruhak, M McDermott, C Wiseman, M Taborn, J Vaglica, E Carter, Motorola, Inc , Austin, TX
-------------------♦-------------------
THURSDAY AFTERNOON Friars/Padre/Sierra Session 24 PAP
VIDEO AND IMAGE PROCESSING SYSTEM ICS
Chairman: L Christopher
Co-Chairman: F Yassa
1:00 A Mixed Analog/Digital Video Signal Processing LSI With On-Chip AD and DA Converters 24 1
Y Okada*, T Matsuura*, T Shinmi*, Y Matsumoto**, H Nishijima***, M Masuda***, S Ueda****, Hitachi
Central Research Lab, Tokyo, Japan*; Hitachi Semiconductor amp; 1C Div , Tokyo, Japan**; Hitachi Consumer
Research Center, Yokohama, Japan***; Hitachi Takasaki Works, Gunma, Japan****
1:25 A Digital Video ßignal Post-Processor for Color Image Sensors 24 2
L J D’Luna, K A Parulski, D C Maslyn, M A Hadley, T J Kenney, R H Hibbard, R M Guidash, P P Lee, C N
Anagnostopoulos, Eastman Kodak Co , Rochester, NY
1:50 A Programmable 1400 MOPS Video Signal Processor 24 3
C M Huizer, K Baker, R Mehtani, J de Block, H Dijkstra, P J Hynes, J Lammerts, M M Lecoutere, A Popp,
AHM van Roermund, P Sheridan, R J Sluyter, FPJM Welten, Philips Research Lab, Eindhoven, The
Netherlands
2:15 A 30 nS (600 MOPS) Image Processor with a Reconfigurable Pipeline Architecture 24 4
K Aono, M Toyokura, T Araki, Matsushita Electrical Industrial Co Ltd , Moriguchi, Japan
2:40 The Design and Implementation of the IMS A110 Image and Signal Processor 24 5
S R Barraclough, M Sotheran, K Bürgin, A P Wise, A Vadher, W P Robbins, R M Forsyth, INMOS Ltd , Bristol,
U K
3:05 A High Speed Outline Font Rasterizing LSI 24 6
N Kai, T Minagawa, I Nagashima, M Ohhashi, Toshiba Corp , Kawasaki, Japan
♦
s
CONTENTS
THURSDAY AFTERNOON____________________________Golden West_________________Sesstion25 PAPER
AMPLIFIERS AND FILTERS
Chairman: C Anagnostopoulos
Co-Chairman: I Scott
1:00 Programmable, Four-Channel, 128-Sample, 40-Ms/s Analog-Ternary Correlator 25 1
|
any_adam_object | 1 |
author_corporate | Custom Integrated Circuits Conference San Diego, Calif |
author_corporate_role | aut |
author_facet | Custom Integrated Circuits Conference San Diego, Calif |
author_sort | Custom Integrated Circuits Conference San Diego, Calif |
building | Verbundindex |
bvnumber | BV009246082 |
ctrlnum | (OCoLC)633018946 (DE-599)BVBBV009246082 |
format | Conference Proceeding Book |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01291nam a2200301 c 4500</leader><controlfield tag="001">BV009246082</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">940313s1989 |||| 10||| und d</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)633018946</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV009246082</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">und</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-29T</subfield><subfield code="a">DE-83</subfield></datafield><datafield tag="111" ind1="2" ind2=" "><subfield code="a">Custom Integrated Circuits Conference</subfield><subfield code="n">11</subfield><subfield code="d">1989</subfield><subfield code="c">San Diego, Calif.</subfield><subfield code="j">Verfasser</subfield><subfield code="0">(DE-588)5043648-X</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Proceedings of the IEEE 1989 Custom Integrated Circuits Conference</subfield><subfield code="b">Town & Country Hotel, San Diego, Calif., May 15 - 18, 1989</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">San Diego, Calif.</subfield><subfield code="c">1989</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">Getr. Zählung</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)1071861417</subfield><subfield code="a">Konferenzschrift</subfield><subfield code="y">1989</subfield><subfield code="z">San Diego Calif.</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">HEBIS Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006152399&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-006152399</subfield></datafield></record></collection> |
genre | (DE-588)1071861417 Konferenzschrift 1989 San Diego Calif. gnd-content |
genre_facet | Konferenzschrift 1989 San Diego Calif. |
id | DE-604.BV009246082 |
illustrated | Not Illustrated |
indexdate | 2024-07-09T17:33:49Z |
institution | BVB |
institution_GND | (DE-588)5043648-X |
language | Undetermined |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006152399 |
oclc_num | 633018946 |
open_access_boolean | |
owner | DE-29T DE-83 |
owner_facet | DE-29T DE-83 |
physical | Getr. Zählung |
publishDate | 1989 |
publishDateSearch | 1989 |
publishDateSort | 1989 |
record_format | marc |
spelling | Custom Integrated Circuits Conference 11 1989 San Diego, Calif. Verfasser (DE-588)5043648-X aut Proceedings of the IEEE 1989 Custom Integrated Circuits Conference Town & Country Hotel, San Diego, Calif., May 15 - 18, 1989 San Diego, Calif. 1989 Getr. Zählung txt rdacontent n rdamedia nc rdacarrier Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1989 San Diego Calif. gnd-content Integrierte Schaltung (DE-588)4027242-4 s DE-604 HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006152399&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
spellingShingle | Proceedings of the IEEE 1989 Custom Integrated Circuits Conference Town & Country Hotel, San Diego, Calif., May 15 - 18, 1989 Integrierte Schaltung (DE-588)4027242-4 gnd |
subject_GND | (DE-588)4027242-4 (DE-588)1071861417 |
title | Proceedings of the IEEE 1989 Custom Integrated Circuits Conference Town & Country Hotel, San Diego, Calif., May 15 - 18, 1989 |
title_auth | Proceedings of the IEEE 1989 Custom Integrated Circuits Conference Town & Country Hotel, San Diego, Calif., May 15 - 18, 1989 |
title_exact_search | Proceedings of the IEEE 1989 Custom Integrated Circuits Conference Town & Country Hotel, San Diego, Calif., May 15 - 18, 1989 |
title_full | Proceedings of the IEEE 1989 Custom Integrated Circuits Conference Town & Country Hotel, San Diego, Calif., May 15 - 18, 1989 |
title_fullStr | Proceedings of the IEEE 1989 Custom Integrated Circuits Conference Town & Country Hotel, San Diego, Calif., May 15 - 18, 1989 |
title_full_unstemmed | Proceedings of the IEEE 1989 Custom Integrated Circuits Conference Town & Country Hotel, San Diego, Calif., May 15 - 18, 1989 |
title_short | Proceedings of the IEEE 1989 Custom Integrated Circuits Conference |
title_sort | proceedings of the ieee 1989 custom integrated circuits conference town country hotel san diego calif may 15 18 1989 |
title_sub | Town & Country Hotel, San Diego, Calif., May 15 - 18, 1989 |
topic | Integrierte Schaltung (DE-588)4027242-4 gnd |
topic_facet | Integrierte Schaltung Konferenzschrift 1989 San Diego Calif. |
url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006152399&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
work_keys_str_mv | AT customintegratedcircuitsconferencesandiegocalif proceedingsoftheieee1989customintegratedcircuitsconferencetowncountryhotelsandiegocalifmay15181989 |