A cache coherence scheme with fast selective invalidation:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Urbana, Ill.
1988
|
| Schriftenreihe: | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report
714 |
| Schlagworte: | |
| Beschreibung: | 8 S. |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV009245725 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 940313s1988 |||| 00||| eng d | ||
| 035 | |a (OCoLC)20082552 | ||
| 035 | |a (DE-599)BVBBV009245725 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-29T | ||
| 100 | 1 | |a Cheong, Hoichi |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a A cache coherence scheme with fast selective invalidation |c Hoichi Cheong and Alexander Veidenbaum |
| 264 | 1 | |a Urbana, Ill. |c 1988 | |
| 300 | |a 8 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |v 714 | |
| 650 | 4 | |a Multiprocessors | |
| 700 | 1 | |a Veidenbaum, Alexander V. |e Verfasser |4 aut | |
| 830 | 0 | |a Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |v 714 |w (DE-604)BV008930033 |9 714 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-006152071 | ||
Datensatz im Suchindex
| _version_ | 1804123692985221120 |
|---|---|
| any_adam_object | |
| author | Cheong, Hoichi Veidenbaum, Alexander V. |
| author_facet | Cheong, Hoichi Veidenbaum, Alexander V. |
| author_role | aut aut |
| author_sort | Cheong, Hoichi |
| author_variant | h c hc a v v av avv |
| building | Verbundindex |
| bvnumber | BV009245725 |
| ctrlnum | (OCoLC)20082552 (DE-599)BVBBV009245725 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00995nam a2200289 cb4500</leader><controlfield tag="001">BV009245725</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">940313s1988 |||| 00||| eng d</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)20082552</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV009245725</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-29T</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Cheong, Hoichi</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">A cache coherence scheme with fast selective invalidation</subfield><subfield code="c">Hoichi Cheong and Alexander Veidenbaum</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Urbana, Ill.</subfield><subfield code="c">1988</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">8 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report</subfield><subfield code="v">714</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Multiprocessors</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Veidenbaum, Alexander V.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report</subfield><subfield code="v">714</subfield><subfield code="w">(DE-604)BV008930033</subfield><subfield code="9">714</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-006152071</subfield></datafield></record></collection> |
| id | DE-604.BV009245725 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:33:49Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006152071 |
| oclc_num | 20082552 |
| open_access_boolean | |
| owner | DE-29T |
| owner_facet | DE-29T |
| physical | 8 S. |
| publishDate | 1988 |
| publishDateSearch | 1988 |
| publishDateSort | 1988 |
| record_format | marc |
| series | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |
| series2 | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |
| spelling | Cheong, Hoichi Verfasser aut A cache coherence scheme with fast selective invalidation Hoichi Cheong and Alexander Veidenbaum Urbana, Ill. 1988 8 S. txt rdacontent n rdamedia nc rdacarrier Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report 714 Multiprocessors Veidenbaum, Alexander V. Verfasser aut Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report 714 (DE-604)BV008930033 714 |
| spellingShingle | Cheong, Hoichi Veidenbaum, Alexander V. A cache coherence scheme with fast selective invalidation Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report Multiprocessors |
| title | A cache coherence scheme with fast selective invalidation |
| title_auth | A cache coherence scheme with fast selective invalidation |
| title_exact_search | A cache coherence scheme with fast selective invalidation |
| title_full | A cache coherence scheme with fast selective invalidation Hoichi Cheong and Alexander Veidenbaum |
| title_fullStr | A cache coherence scheme with fast selective invalidation Hoichi Cheong and Alexander Veidenbaum |
| title_full_unstemmed | A cache coherence scheme with fast selective invalidation Hoichi Cheong and Alexander Veidenbaum |
| title_short | A cache coherence scheme with fast selective invalidation |
| title_sort | a cache coherence scheme with fast selective invalidation |
| topic | Multiprocessors |
| topic_facet | Multiprocessors |
| volume_link | (DE-604)BV008930033 |
| work_keys_str_mv | AT cheonghoichi acachecoherenceschemewithfastselectiveinvalidation AT veidenbaumalexanderv acachecoherenceschemewithfastselectiveinvalidation |