The importance of prepass code scheduling for superscalar and superpipelined processors:

Abstract: "Superscalar and superpipelined processors provide hardware that has the ability to execute many instructions in parallel. In order for this potential to be translated into the speedup of real programs, the compiler must be able to schedule instructions so that they can be overlapped...

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Bibliographic Details
Main Authors: Chang, Pohua P. (Author), Lavery, Daniel M. (Author), Hwu, Wen-mei W. (Author)
Format: Book
Language:English
Published: Urbana, Ill. 1991
Series:Center for Supercomputing Research and Development <Urbana, Ill,>: CSRD report 1144
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Summary:Abstract: "Superscalar and superpipelined processors provide hardware that has the ability to execute many instructions in parallel. In order for this potential to be translated into the speedup of real programs, the compiler must be able to schedule instructions so that they can be overlapped without interlock delays and resource conflicts. Previous work has shown that prepass code scheduling helps to produce a better schedule for scientific programs. But the importance of prescheduing has never been demonstrated for control-intensive non- numerical programs. These programs are significantly different from the scientific programs because they contain frequent branches and they require global scheduling in order to find enough independent instructions
In this paper, the code scheduler of the IMPACT-I C compiler is described and used to study the importance of prepass code scheduling for a set of production C programs. It is shown that, in contrast to the results previously obtained for scientific programs, prescheduling is not important for compiling control-intensive programs to the current generation of superscalar and superpipelined processors. However, if some of the current restrictions on upward code motion are removed in future architectures, prescheduling substantially improves the execution time of this class of programs on both superscalar and superpipelined processors.
Physical Description:47 S.

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