Verfügbarkeit: The proceedings of the European Conference on Design Automation

The proceedings of the European Conference on Design Automation: Amsterdam, The Netherlands, 25 - 28 February 1991

Gespeichert in:

Bibliographische Detailangaben
Körperschaft:	EDAC Amsterdam (VerfasserIn)
Format:	Tagungsbericht Buch
Sprache:	English
Veröffentlicht:	Washington, DC u.a. IEEE Computer Soc. Pr. 1991
Schlagworte:	CAD Konferenzschrift > 25.02.1991-28.02.1991 > Amsterdam
Online-Zugang:	Inhaltsverzeichnis
Beschreibung:	XXIV, 601 S. graph. Darst.

Internformat

MARC


LEADER	00000nam a2200000 c 4500
001	BV008984035
003	DE-604
005	20220207
007	t
008	940206s1991 d\|\|\| \|\|\|\| 10\|\|\| eng d
020			\|z 0818621302 \|9 0-8186-2130-2
035			\|a (OCoLC)180088788
035			\|a (DE-599)BVBBV008984035
040			\|a DE-604 \|b ger \|e rakddb
041	0		\|a eng
049			\|a DE-29T \|a DE-91
084			\|a ELT 035f \|2 stub
111	2		\|a EDAC \|n 2 \|d 1991 \|c Amsterdam \|j Verfasser \|0 (DE-588)5090854-6 \|4 aut
245	1	0	\|a The proceedings of the European Conference on Design Automation \|b Amsterdam, The Netherlands, 25 - 28 February 1991
264		1	\|a Washington, DC u.a. \|b IEEE Computer Soc. Pr. \|c 1991
300			\|a XXIV, 601 S. \|b graph. Darst.
336			\|b txt \|2 rdacontent
337			\|b n \|2 rdamedia
338			\|b nc \|2 rdacarrier
650	0	7	\|a CAD \|0 (DE-588)4069794-0 \|2 gnd \|9 rswk-swf
655		7	\|0 (DE-588)1071861417 \|a Konferenzschrift \|y 25.02.1991-28.02.1991 \|z Amsterdam \|2 gnd-content
689	0	0	\|a CAD \|0 (DE-588)4069794-0 \|D s
689	0		\|5 DE-604
856	4	2	\|m HEBIS Datenaustausch \|q application/pdf \|u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005934084&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA \|3 Inhaltsverzeichnis
999			\|a oai:aleph.bib-bvb.de:BVB01-005934084

Datensatz im Suchindex

_version_	1804123323729182720
adam_text	The Proceedings of The European Conference on Design Automation rmstadt inc N Table of Contents Foreward eesessonesssensensensonsnnnssnunsnnssnnennsnnnannsensenseensntonentontssssnssssnsssssanesenessnensnnsenssserenenennensenunsansssnnsansnene v Conference Committee uu neee i Technical Program Committce Tutorials Keynote Presentations cccsscessssceecnsseseeseseesssceverscesressssesssospsesesesessossaseses xi EDAC 92 Call for Papers cccccsccscscsseneccveescreceesseaseseaseseecececaaeuaneneasssesstsssssessaseteesevsetaseeuserace xiii Panel Session: Push-Button or Interactive Analogue Design? nsnneenesennenssssnssnenennensesnnensnersensonnenennensnssassensnernsnnennenenne 1 Chairman: W Sansen, KU Leuven, Belgium Panel: M Degrauwe, CSEM, Switzerland M Declerck, EPFL, Lausanne, Switzerland W Van Bokhoven, Eindhoven, The Netherlands C Wouda, Philips, The Netherlands L Moore, Anacad, FRG Session 1B: Formal Verification Techniques Moderators: Hans Eveking, Technische Hochschule, Darmstadt, FRG Christian Berthet, Bull, France 1B 1 Fast Functional Evaluation of Candidate OBDD Variable Orderings DERoss, KM Butler, R Kapur, M R Mercer 1B 2 Resolution-Based Correctness Proofs of Synchronous Circuits uueeeenenneennessennnnnernenensssnnnrsnsnnennnensnennnnen 11 P Camurati, T Margaria and P Prinetto 1B 3 Correct Interactive Transformational Synthesis of DSP Hardware usessessesssnsnsssorsensannoenserensnossonsannen 16 F P Burns, D J Kinniment and A M Koelmans 1B 4 Verification of Synthesized Circuits at Register Transfer Level with Flow Graphs c:csecscesssseceersenses 22 F Feldbusch and R Kumar Session 1C: Frameworks Moderators: P Dewilde, Delft University of Technology, The Netherlands A]J van der Hoeven, Delft University of Technology, The Netherlands 1C 1 Tool Communication in an Integrated Synthesis Environment -scceceececsesesreesesesnsenacnacasenersesees 28 B Kleinjohann and E Kupitz 1C 2 A Distributed Engineering Database Management System for IC Design csessscssssessssseereeseseseeeseses 33 W Cao, YELien, Y Qiu, L Shao and X Liu XV 1C 3 An Approach to Design Flow Management in CAD FrameworksS csesscccssesssccesecceseceserecerroeesersaseres 38 M Mehendale 1C 4 Why to Incorporate a Data Definition Language into a CAD Frameworks Extension Language un 43 K Groning and W Heijenga Session 2A: Logic Synthesis Moderators: F Poirot, VLSI Technology, France F Theeuwen, Eindhoven University, The Netherlands 2A 1 On Variable Ordering of Binary Decision Diagrams for the Application of Multi- level Logic Synthesis eessesonesonensnennnessnenosnnsrnessonsnensnennessonsorsnnnnnonsennsonessonennnonenersssontessnes netten M Fujita, Y Matsunaga and T Kakuda 2A 2 PHIFACT - A Design Space Exploration Program : :ccccsscccecceceessenececensscecucuneneaneesescessanenaeeseeeees 55 F Crowet, M Davio, C Dierieck, J Durieu, G Louis and C Ykman-Couvreur 2A 3 Synthesis of Multi-Level Logic with One Symbolic Input esnnesssnnnenennaonsonnsunenennonnnerssonnsen en ertre 60 F Buijs and T Lengauer 2A 4 PLATO: A CAD Tool for Logic Synthesis Bascd on Decomposition enensennsenenenennennnnensenesonnr on snenne onen 65 T Luba, J Kalinowski and K Jasinski Session 2B: Fault Modelling and Test Generation Moderators: B Courtois, TIM3/IMAG, France EJ Aas, Norwegian Institute of Technology, Norway 2B 1 An Approach to the Analysis and Test of Crosstalk Faults in Digital VLSI Circuits ssereesesevereeres 72 A Rubio, N ltazaki, X Xu and K Kinoshita 2B 2 Detection of PLA Multiple Crosspoint Faults ccsscsccssssseressnensecesnncececesesseserscsenerseenersnepenengees 80 M Ambanelli, M Favalli, P Olivo and B Ricco 2B 3 A Probabilistic Fault Model For Analog Faults :sccssssscceseccersssecseescesssoanaesercesesesecesesesereeeeeet 85 M Favalli, P Olivo and B Ricco 2B 4 The Automatic Diagnosis of Faults in Analogue and Mixed-Signal Circuits cssscesccesessereneeesaneeene 89 A McKeon and A Wakeling Session 2C: Layout Analysis Moderators: P Capocelli, SGS-Thomson, Italy D Wilcock, Plessey, UK 2C 1 Formal Sizing Rules Of CMOS Circuits :cscsssssssssssecessstenacesnseceenaesecuaccecesonsouaneasenesenseaaueners 96 D Auvergne, N Azemard, V Bonzom, D Deschacht and M Robert 2C 2 Delay Estimation for CMOS Functional Cells 0 c ccccsssssssssscsssssccssccncesesssnseessessnenesereseseestesseess 101 J Madsen xvi 2C 3 Electrical Modelling of Lossy On-Chip Multilevel Interconnecting Lines cccscssosssssesssesessesserssesseees 106 K Z Dimopoulos, J N Avaritsiotis and S J White 2C 4 Restructuring VLSI Layout Representations for ESficicncy sscsecsssrssressscsescarscessssecececeeoeenensesessecs 1 R Navir, R Chamberlain and V Chickermane Session 3A: Data Path Synthesis Moderators: W Rosensticl,Universitat Karlsruhe, FRG R Camposano, IBM, USA 3A 1 Address Generation for Array Access, Based on Modulus m Counters ccccccscccseccececesesssssssssenseneceens 118 DM Grant and P B Denyer 3A 2 High Level Synthesis: A Data Path Partitioning Method Dedicated To Specd Enhancement ssser0e 123 F Monteiro, B Rouzeyre and G Sagnes 3A 3 Datapath Optimization Using Feedback c sssssssecccercccecnseseceessescensseescsesscssasssscnsceeensnsesseseeeanoags 129 D Knapp Session 3B: Circuit Simulation and Macromodelling Moderators: L Nederlof, Philips, The Netherlands L Vidigal, INESC, Portugal 3B 1 Eldo-XL: A Software Accelerator for the Analysis of Digital MOS Circuits by an Analog Simulator 136 J Besnard, J Benkoski and B Hennion 3B 2 SWEC: A StepWise Equivalent Conductance Timing Simulator for CMOS VLSI Circuits u 142 S Lin, M Marek-Sadowska and E Kuh 3B 3 Circuit Partitioning for Waveform Relaxation ecsssssesssesssneensersnessonensonnenersenann 149 W John, W Rissiek and K L Paap 3B 4 Performance Macromodelling and Optimization Of Regular VLSI Structures ccccsssseseceesserreceseenens 154 P Hallam, T I Pritchard and G C Townsend Session 3C: Partitioning for Layout Moderators: J-P Le Bouquin, JBM, France H Beke, EDC, The Netherlands 3C 1 Glue-Logic Partitioning for Floorplans with a Rectilincar Datapath ee uneansannerennennnonnennennnnsonnonsonssnnnn 162 AC Wu and D Gajski 3C 2 Towards Optimizing Global MinCut Partitioning eeeseesssssaesassnssnessnssnnsensnsnnensensnnssennsnnsansansnnene 167 AG Hoffmann 3C 3 Sharp-Looking Geometric Partitioning :csssssccecssseseecsseecssseesestacesesesesegesesepanesscasereeceesenseasenenees 172 S Bapat and J P Cohoon xvii A etna ae nt 3C 4 Partitioning a Network into n Pieces with a Time-Efficient Net Cost Function cccceleeseserensereeoenes 177 P Stravers Session 4A: Finite State Machine Optimisation Moderators: Giovanni de Micheli, Stanford University, USA G Goossens, IMEC, Belgium 4A 1 Exact and Heuristic Algorithms for the Minimization of Incompletely Specified State Machines 184 G D Hachtel, J K Rho, F Somenzi and R Jacoby 4A 2 Fast Heuristic Algorithms For Finite State Machine Minimization ccccsssesrsncscerssersscerseenenenes 192 LN Kannan and D Sarma 4A 3 Formal Method For Self-Timed Design ccssscssssssesssessssscsececsnescssseceseceeseseeense nese nensanenee eee snes 197 M A Kishinevsky, A Yu Kondratyey and A R Taubin 4A 4 Array Folding Using Heuristic and Simulated Annealing csssssssscsssssseneeessssrserseenssssnnsaeeesne sneer 202 LN Kannan and D Sarma Session 4B: Test Pattern Generation and Diagnosis Moderators: A Ambler, Brunel University, UK G Saucier, JMAG, France 4B 1 Automated Test Pattern Generation for the Cathedral-I1/2nd Architectural Synthesis Environment +- 208 J van Sas, F Catthoor, P Vandeput, F Rossaert and H De Man 4B 2 HITEC: A Test Generation Package for Sequential Circuits cecccsccseercereeseseeececneeensunaeneeesneoas 214 T Niermann and J H Patel 4B 3 On The Selection Of A Partial Scan Path With Respect To Target Faults cccccssssccceesereeesneeeeesseene 219 H Gundlach, B Koch and K D Muller-Glaser 4B 4 Model-Based Fault Diagnosis of Sequential Circuits and Its Acceleration ccseeessceesnrceseseneneesees 224 B R-Favila, A Wakeling and PYK Cheung Session 4C: Routing Moderators: G Koetzle, JBM, FRG R Zuelle, JBM, FRG 4C 1 An Algorithm for Improving Optimal Placement for River-Routing cseccssesscsessesessenescesensenserenees 232 S Healey 4C 2 An Integrated Layout System for Sca-of-Gates Module Gencralion nneeausssnnnesesensnonnsnnnenensnnanoorneneren en 237 P Duchene, M Declerg and S M Kang 4C 3 A Global Router For Sea-Of-Gates Circuis scssscssscscsccsesssscsseseccsscessousensesssesssnecssessnceseeneseeerns 242 K-W Lee and C Sechen xviii 4C 4 Mickey: A Macro Cell Global Router :ccsscssssssssssssssssstentevecsssssssaceserensscsuesenseceasessesonsenseseees 248 D Chen and C Sechen Panel Session: What Do Designers Expect of Future CAD System? 0 ccccssesssssescssssessessesseneeseosenecseuesucacsesssesnenacseconssnsneesesaesens 253 Chairman: H De Man, IMEC/KU Leuven, Belgium Panel: E Roza, Philips Research Labs, The Netherlands W Glauert, Bosch, FRG M Strafner, Siemens, FRG M Rahier, Alcatel-Bell, Belgium J Hammock, Mentor Graphics, UK C Adams, EuCAD, UK Session 5B: Timing Verification and Specification Moderators: P Prinetto, Politecnico di Torino, Italy M Fujita, Fujitsu, Japan 5B 1 TATOO: An Industrial Timing Analyzer with False Path Elimination and Test Pattern Generation J Benkoski and R B Stewart 5B 2 TAS: An Accurate Timing Analyser for CMOS VLSI neassssssnssnssssossansnnansnnssnannenesnsnonnnnenanenn 261 A Hajjar, R Marbot, A Greiner and P Kiani 5B 3 A Hierarchical Approach to Timing Verification in CMOS VLSI Design -sscssssecscesaeeessssessesers 266 H G Yang and D M Holburn 5B 4 Clock Independent Timing Verification of Level-Sensitive Latches :csccssssessscsesccccnecesecereseeecneeeeoes 271 R Tjarnstrom Session 5C: Synthesis of Testable Circuits Moderators: G Saucier, /MAG, France A Ambler, Brunel University, UK 5C 1 Test Scheduling and Controller Synthesis in the CADDY-System uueeseessesssssnsnnnnnnnnnnsenensnneonssnneneen 278 M Rudolph, M Neher andW Rosenstiel 5C 2 Synthesis of Fully Testable Sequential Machines : 0ssesceccceeeceeeeesecevsevesseeesessesesessesaueaearaaees 283 R Thomas and § Kundu 5C 3 MACHETE: Synthesis of Sequential Machines for Easy Testability ccccceceseeeseesesssesensesesenenens 289 B Vinnakota and N K Jha 5C 4 Testability Analysis of Hierarchical Finite State Machines seeseneeensennesenenesnenennnenenennonenenenennonnasen 294 F Mariinolle, J-C Geoffroy and B Soulas xix Session 6A: Scheduling and Allocation Moderators: G Goosens, /MEC, Belgium G de Micheli, Stanford University, USA 6A 1 Area and Performance Optimizations in Path-Based Scheduling 22er sonen nsnnnneoenannennen nenne nenne 304 RA Bergamaschi, R Camposano and M Payer 6A 2 CASCH - a Scheduling Algorithm for “High Level” - Synthesis 200000002nnnennnennnennnnnnnnesnenn ner 311 P Gutberlet, H Kramer and W Rosenstiel 6A 3 Specification of Timing Constraints for Controller Synthesis ::sssssscscesseeresesersenseeosenrensereres 316 R Zahir and W Fichtner Session 6B: Switch-Level Simulation Moderators: M Heydeman, ES2, France C Newton, RSRE, UK 6B 1 Parallel Switch-Level Simulation for VLST euesenesenaonessnnnsssensunnunnenssnnnensnnnnanenennenennor nass rss sent 324 RB Mueller-Thuns, D G Saab and J A Abraham 6B 2 Functional Abstraction of Logic Gates For Switch-Level Simulation neersnnenerssonnnsensenenennansensnene nen 329 DT Blaauw, D G Saab, P Banerjee and J A Abraham 6B 3 Incremental Switch-Level Simulation with Zeroffnteger-Delay unesensnennsunsensnnnnenenenenonennansnntesen nenn 334 L Jones 6B 4 On Probabilistic Switch-Level Simulation for Asynchronous CircuilS nesesssersenssesesenseenneenonnsnaesnenen 339 S Rajgopal and A Tyagi Session 6C: Floorplan Optimization Moderators: R Otten, TU Delft, The Netherlands L van Ginneken, /BM, USA 6C 1 Floorplanning Strategy For Mixed Analog-Digital VLSI Integrated Circuits secccesssrcoreoeaneneeceess 346 L Paris, G Berbel and T Oses 6C 2 LAST: A Layout Area and Shape Function esTimaior for High Level Applications nennen 351 F J Kurdahi and C Ramachandran 6C 3 Efficient Shape Curve Construction in Floorplan Design csscscssssccsssssesnesessoneecetessaresonsoverenarenees 356 T C Wang and D F Wong 6C 4 Goal Oriented Slicing Enumeration Through Shape Function Clipping :ccsscscsescessesertnereeenseees „361 G Sig! and U Schlichtmann Session 7A: Decomposition of Finite State Machines Moderators: F Theeuwen, Eindhoven University, The Netherlands F Poirot, VLSI Technology, France 7A 1 Optimization of Micro-Controllers By Partitioning csssscscsscssssssersssssseceeessrssneecensnseseeeeseees 368 G Tarroux, B Rouzeyre and G Sagnes 1A 2 A New Decomposition Method for Multilevel Circuit Design 374 D Bochmann, F Dresig and B Steinbach 7A 3 Decomposing Data Machines eessonssnessssunesonannnassssnnenunsnensnersnersnnersnnnsssnssnsssnrensonesssenssssnen 378 W Wolf Session 7B: Formal Verification Moderators: J Herbert, SR/ International, UK L Claesen, IMEC, Belgium 7B 1 The VLSI-Programming Language Tangram and its Translation into Handshake Circuits seecccesseee 384 K van Berkel, J Kessels, M Roncken, R Saeijs and F Schalij 7B 2 Translating System Specifications to VHDL cscsssessererecersonsessssnecsenencaeaseanesseseecsenesesneanenseasecs 390 S Narayan, F Vahid and D Gajski 7B 3 Formal Methods for Silicon Compilation T Kalker 7B 4 Data Flow Graphs: System Specification with the Most Unrestricted Semantics ssssssseeseseesesseee 401 GG de Jong Session 7C: System Design Tools Moderators: J P Tual, BULL, France J Brouwers, EDA Systems, USA 7C 1 GENVIEW: A Portable Source-Level Debugger For MacroCell Generators senessseeosessensnsossansnenunennne 408 A Compan, A Greiner, F Pecheux and F Petrot 7C 2 A Framework for Hierarchical Performance Analysis c::ssscsssssssscscscsoesensrsnserescseussceveseseeeseaser enees 413 F M Saadi and B Kaminska 7C 3 HERESY: A Hybrid Approach to Automatic Schematic Generation uesesonanersosssnsnsssnssonnnnasnsenerunnsennt 419 T Chiueh 7C 4 GRTL - A Graphical Platform For Pipelined System Design us0snsssensnsossaenenenenenanssnnnsnensnnessnenennn 424 G Jennings xxi Session 8A: Synthesis for High-Speed Applications Modcrators: R Camposano, IBM, USA W Rosenstiel, Universitat Karlsruhe, FRG 8A 1 Improved Force-Directed Scheduling csccssssscesecsssecessssssessssssassesssensessssesseoeessessessesssresersersesee WFJ Verhaegh, EHL Aarts, JHM Korst and PER Lippens 8A 2 PHIDEO: A Silicon Compiler for High Speed Algorithms cccccccccccsssssscsesessscseessessesnssseseneeeeere P ER Lippens, J van Meerbergen, A van der Werf, W Verhaegh, B McSweeney, J Huisken and O McArdle : 8A 3 Affine Transformations for Multi-Dimensional Signal Processing on ASIC Regular Arrays re 442 J Rosseel, M van Swaaij, F Catthoor and Hugo de Man Session 8B: Object Oriented Approaches and Modelling Moderators: E van Utteren, Philips, The Netherlands H Kahn, University of Manchester, UK 8B 1 Switch and Logic-level Modeling in EDIF 200 - Limitations and Proposed Solutions s :esseeeeereees 448 SR Mukherjee and M Mannan 8B 2 Design of a Persistent Programming Environment in an Object Oriented Language Using Clustering and Composite Objects eesssssesennsessensnssnssnnsunnsnnenssnnennanasnnssanznsnessernnsnsnnesnnnnse 453 MN Sim and PM Dewilde 8B 3 A Hardware Design System Based on Object-Oriented Principles ccccccccscsssenenceeceeeceseseeseeecenereees 459 AJ van der Hoeven, P van Prooijen, E F Deprettere and P M Dewilde 8B 4 Design by Similarity Using Transaction Modeling and Statistical Techniques seccccesersereceeeeneeeeee! 464 A Kabbaj, E Cerny, M Dagenais and F Bouthillier Session 8C: Analogue Design and Layout Moderators: L Moore, Anacad, FRG W van Bokhoven, TU Eindhoven, The Netherlands 8C 1 An Automatic Synthesizer for CMOS Operational Amplifiers ueeesessssnessunnenaonsennseenennennnneenensasnnnnanne 470 C-Y Kuo, L-G Chen and T-M Parng 8C 2 DONALD - A Workbench for Interactive Design Space Exploration and Sizing of Analog Circuits 475 K Swings and W Sansen 8C 3 A New Approach To Layout of Custom Analog Cells 480 L-O Donzelle and P-F Dubois 8C 4 Interactive Symbolic Distortion Analysis of Analogue Integrated CircuißS eeenerenensenessnnnennensnnnnannenennen 484 P Wambacq, G Gielen and W Sansen Panel Session: Formal Hardware Verification Myth or Reality? ueueesensenmensmmseersenssenssnsesesnsessensenssessenssnssnsenssnnsenenennenennnenne 489 Chairman: G Saucier, NPG, France Panel: F Anceau, Bull, France L Claesen, IMEC, Belgium J A Darringer, JBM, USA M Fourman, University of Edinburgh, UK F Poirot, VLSI Technology, France Session 9B: Test Pattern Generation for Combinational Circuits Moderators: A Rubio, Balearic Islands University, Spain B Courtois, T/M3/IMAG, France 9B 1 Symbolic Implication In Test Generation csssscccccsssssscssnseaesecesreessseensesesccersesetserscensessesesrsee 492 S Kundu, I Nair, L Huisman and V Iyengar 9B 2 Structure Based Methods for Parallel Pattern Fault Simulation in Combinational Circuits :0se0 497 B Becker, R Hahn, R Krieger and U Sparmann 9B 3 Experiments with Autonomous Test Of PLAS ccccssssssssscsrestsssersesrseseesasressescessnesassseseseseree 503 EJ Aas and G Nystu 9B 4 A Self-Checking PLA Automatic Generator Tool Based on Unordered Codes Encoding snesnessennennen 510 K Torki, M Nicolaidis and A O Fernandes Session 9C: Partitioning Techniques for CAD Moderators: F Catthoor, IMEC, Belgium J van Eijndhoven, Eindhoven University ofTechnology, The Netherlands 9C 1 Circuit Parütioning into Small Sets: a Tool to Support Testing with Further Applications 518 S Tragoudas, R Farrell and F Makedon 9C 2 Iterative Compaction: An Improved Approach To Graph And Circuit Bisection essersenensnneresnannnsneenennenr 523 J Haralambides and F Makedon 9C 3 On L xn Boolean Matrices with All Lxk Submatrices Having 2* Distinct Row Vectors 528 H Wu Session 10A: Technology Mapping Moderators: LR A Bergamaschi, JBM, USA W Rosenstiel, Universitat Karlsruhe, FRG 10A 1 Technology Mapping for a Two-Output RAM-Based Field Programmable Gate Array c sssssessescee 534 D Filo, J Chih-Yuan Yang, F Mailhot and G De Micheli xxiii 10A 2 A Fast and Efficient Algorithm for Detcrmining Fanout Trees in Large Networks u 53 S Lin and M Marek-Sadowska 10A 3 Optimization Techniques For Multiple Output Function Synthesis :cccccscceceeereeeseseesseeeseesersueey 545 G Buonanno, D Sciuto and R Stefanelli Session 10B: High Performance Simulation Techniques for Digital systems Moderators: S Gai, Politecnico di Torino, Italy P Flake, Eucad, UK 10B 1 Concurrent Min-Max Simulation eesssscsesccesevenssecscecseossceccesnecessccacececeoeeecesecsensananaageageeaneeyen 554 E Ulrich, K P Lentz, S Demba and R Razdan 10B 2 Hybrid Compiled/Interpreted Simulation of MOS Circuits cccccccccscecsseeesensncercosnenssnseaeosensneeren 558 L McMurchie, C Anderson and G Borriello 10B 3 Periodic Signal Suppression in a Concurrent Fault Simulator uneeesesesesennnnnonsenersennenenssnnenen nennen 565 T Weber and F Somenzi 10B4 A Hardware Fault Simulation Engine unansssesesmessesesnnnsnennonennenensnenanenaensnennennnenensnrnrorernnenn 570 D Cock and A Carpenter Session 10C: Layout Tools Moderator: J Frehel, SGS-Thomson, France 10C 1 A Performance Analysis Tool for Performance-Driven Micro-Cell Generation meneseernenenrennnasesten 576 R Peset Liopis, RJH Koopman, H G Kerkhoff and J A Braat 10C 2 Module Synthesis for Finite State Machines ccsscsssssssssssssssssssssssssesssessssssscseseecsssesesssetesssnecsecenneesse 581 A Keuhlmann and Y Manoli Poster Summaries sssssesernessnseonssenenneneessnnsennnssennenensannnennsnnennennnnennrannnsnesnenensnonnenn 587 Author Index Aaunsnonnsunssnanssnunsnusssnsssonnesnsnnsssnnnnssssnsnsssnsnanennnanneesnönsenanssassssnenssasssnsrensen 599 xxiv
any_adam_object	1
author_corporate	EDAC Amsterdam
author_corporate_role	aut
author_facet	EDAC Amsterdam
author_sort	EDAC Amsterdam
building	Verbundindex
bvnumber	BV008984035
classification_tum	ELT 035f
ctrlnum	(OCoLC)180088788 (DE-599)BVBBV008984035
discipline	Elektrotechnik
format	Conference Proceeding Book
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01327nam a2200325 c 4500</leader><controlfield tag="001">BV008984035</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20220207 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">940206s1991 d\|\|\| \|\|\|\| 10\|\|\| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="z">0818621302</subfield><subfield code="9">0-8186-2130-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)180088788</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV008984035</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-29T</subfield><subfield code="a">DE-91</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 035f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="111" ind1="2" ind2=" "><subfield code="a">EDAC</subfield><subfield code="n">2</subfield><subfield code="d">1991</subfield><subfield code="c">Amsterdam</subfield><subfield code="j">Verfasser</subfield><subfield code="0">(DE-588)5090854-6</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">The proceedings of the European Conference on Design Automation</subfield><subfield code="b">Amsterdam, The Netherlands, 25 - 28 February 1991</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Washington, DC u.a.</subfield><subfield code="b">IEEE Computer Soc. Pr.</subfield><subfield code="c">1991</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXIV, 601 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)1071861417</subfield><subfield code="a">Konferenzschrift</subfield><subfield code="y">25.02.1991-28.02.1991</subfield><subfield code="z">Amsterdam</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">HEBIS Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005934084&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-005934084</subfield></datafield></record></collection>
genre	(DE-588)1071861417 Konferenzschrift 25.02.1991-28.02.1991 Amsterdam gnd-content
genre_facet	Konferenzschrift 25.02.1991-28.02.1991 Amsterdam
id	DE-604.BV008984035
illustrated	Illustrated
indexdate	2024-07-09T17:27:57Z
institution	BVB
institution_GND	(DE-588)5090854-6
language	English
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-005934084
oclc_num	180088788
open_access_boolean
owner	DE-29T DE-91 DE-BY-TUM
owner_facet	DE-29T DE-91 DE-BY-TUM
physical	XXIV, 601 S. graph. Darst.
publishDate	1991
publishDateSearch	1991
publishDateSort	1991
publisher	IEEE Computer Soc. Pr.
record_format	marc
spelling	EDAC 2 1991 Amsterdam Verfasser (DE-588)5090854-6 aut The proceedings of the European Conference on Design Automation Amsterdam, The Netherlands, 25 - 28 February 1991 Washington, DC u.a. IEEE Computer Soc. Pr. 1991 XXIV, 601 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 25.02.1991-28.02.1991 Amsterdam gnd-content CAD (DE-588)4069794-0 s DE-604 HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005934084&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	The proceedings of the European Conference on Design Automation Amsterdam, The Netherlands, 25 - 28 February 1991 CAD (DE-588)4069794-0 gnd
subject_GND	(DE-588)4069794-0 (DE-588)1071861417
title	The proceedings of the European Conference on Design Automation Amsterdam, The Netherlands, 25 - 28 February 1991
title_auth	The proceedings of the European Conference on Design Automation Amsterdam, The Netherlands, 25 - 28 February 1991
title_exact_search	The proceedings of the European Conference on Design Automation Amsterdam, The Netherlands, 25 - 28 February 1991
title_full	The proceedings of the European Conference on Design Automation Amsterdam, The Netherlands, 25 - 28 February 1991
title_fullStr	The proceedings of the European Conference on Design Automation Amsterdam, The Netherlands, 25 - 28 February 1991
title_full_unstemmed	The proceedings of the European Conference on Design Automation Amsterdam, The Netherlands, 25 - 28 February 1991
title_short	The proceedings of the European Conference on Design Automation
title_sort	the proceedings of the european conference on design automation amsterdam the netherlands 25 28 february 1991
title_sub	Amsterdam, The Netherlands, 25 - 28 February 1991
topic	CAD (DE-588)4069794-0 gnd
topic_facet	CAD Konferenzschrift 25.02.1991-28.02.1991 Amsterdam
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005934084&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT edacamsterdam theproceedingsoftheeuropeanconferenceondesignautomationamsterdamthenetherlands2528february1991

Verfügbarkeit

Es ist kein Print-Exemplar vorhanden.

Fernleihe Bestellen Achtung: Nicht im THWS-Bestand! Inhaltsverzeichnis

MARC

Datensatz im Suchindex

Es ist kein Print-Exemplar vorhanden.

Ähnliche Einträge