Comparing parallelism extraction techniques: superscalar processors, pipelined processors, and multiprocessors
Abstract: "We compare the ability of a superscalar processor, a pipelined processor, and a multiprocessor, all with the same degree of architectural parallelism, to automatically extract parallelism from scientific application programs. We find that the loop-level parallelism of the multiproces...
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Urbana, Ill.
1990
|
| Series: | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report
954 |
| Subjects: | |
| Summary: | Abstract: "We compare the ability of a superscalar processor, a pipelined processor, and a multiprocessor, all with the same degree of architectural parallelism, to automatically extract parallelism from scientific application programs. We find that the loop-level parallelism of the multiprocessor performs better than the instruction-level parallelism of the other processors on programs with high inherent parallelism. This performance difference is due to register allocation difficulties and instruction look-ahead requirements in the superscalar and pipelined processors The results suggest that dynamic loop unrolling is inadequate for obtaining the best performance in these processors and that it should be done by the compiler to allow for more intelligent register allocation. The multiprocessor is shown to have generally the highest memory and functional unit bandwidth requirements while the pipelined processor requires significantly more registers in order to hide the memory latency as efficiently as the other configurations. We show that there is significant fine-grain parallelism within parallel loop iterations as well as in the sequential code between parallel loops. Hence, a combination of fine-grain and coarse-grain parallelism extraction techniques are necessary in order to maximize performance. |
| Physical Description: | 32 S. |
Staff View
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| 245 | 1 | 0 | |a Comparing parallelism extraction techniques |b superscalar processors, pipelined processors, and multiprocessors |c David J. Lilja ; Pen-Chung Yew |
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| 490 | 1 | |a Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |v 954 | |
| 520 | 3 | |a Abstract: "We compare the ability of a superscalar processor, a pipelined processor, and a multiprocessor, all with the same degree of architectural parallelism, to automatically extract parallelism from scientific application programs. We find that the loop-level parallelism of the multiprocessor performs better than the instruction-level parallelism of the other processors on programs with high inherent parallelism. This performance difference is due to register allocation difficulties and instruction look-ahead requirements in the superscalar and pipelined processors | |
| 520 | 3 | |a The results suggest that dynamic loop unrolling is inadequate for obtaining the best performance in these processors and that it should be done by the compiler to allow for more intelligent register allocation. The multiprocessor is shown to have generally the highest memory and functional unit bandwidth requirements while the pipelined processor requires significantly more registers in order to hide the memory latency as efficiently as the other configurations. We show that there is significant fine-grain parallelism within parallel loop iterations as well as in the sequential code between parallel loops. Hence, a combination of fine-grain and coarse-grain parallelism extraction techniques are necessary in order to maximize performance. | |
| 650 | 4 | |a Multiprocessors |x Evaluation | |
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| 830 | 0 | |a Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |v 954 |w (DE-604)BV008930033 |9 954 | |
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Record in the Search Index
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| id | DE-604.BV008949514 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:27:18Z |
| institution | BVB |
| language | English |
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| physical | 32 S. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
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| series | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |
| series2 | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |
| spelling | Lilja, David J. Verfasser aut Comparing parallelism extraction techniques superscalar processors, pipelined processors, and multiprocessors David J. Lilja ; Pen-Chung Yew Urbana, Ill. 1990 32 S. txt rdacontent n rdamedia nc rdacarrier Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report 954 Abstract: "We compare the ability of a superscalar processor, a pipelined processor, and a multiprocessor, all with the same degree of architectural parallelism, to automatically extract parallelism from scientific application programs. We find that the loop-level parallelism of the multiprocessor performs better than the instruction-level parallelism of the other processors on programs with high inherent parallelism. This performance difference is due to register allocation difficulties and instruction look-ahead requirements in the superscalar and pipelined processors The results suggest that dynamic loop unrolling is inadequate for obtaining the best performance in these processors and that it should be done by the compiler to allow for more intelligent register allocation. The multiprocessor is shown to have generally the highest memory and functional unit bandwidth requirements while the pipelined processor requires significantly more registers in order to hide the memory latency as efficiently as the other configurations. We show that there is significant fine-grain parallelism within parallel loop iterations as well as in the sequential code between parallel loops. Hence, a combination of fine-grain and coarse-grain parallelism extraction techniques are necessary in order to maximize performance. Multiprocessors Evaluation Yew, Pen-Chung Verfasser aut Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report 954 (DE-604)BV008930033 954 |
| spellingShingle | Lilja, David J. Yew, Pen-Chung Comparing parallelism extraction techniques superscalar processors, pipelined processors, and multiprocessors Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report Multiprocessors Evaluation |
| title | Comparing parallelism extraction techniques superscalar processors, pipelined processors, and multiprocessors |
| title_auth | Comparing parallelism extraction techniques superscalar processors, pipelined processors, and multiprocessors |
| title_exact_search | Comparing parallelism extraction techniques superscalar processors, pipelined processors, and multiprocessors |
| title_full | Comparing parallelism extraction techniques superscalar processors, pipelined processors, and multiprocessors David J. Lilja ; Pen-Chung Yew |
| title_fullStr | Comparing parallelism extraction techniques superscalar processors, pipelined processors, and multiprocessors David J. Lilja ; Pen-Chung Yew |
| title_full_unstemmed | Comparing parallelism extraction techniques superscalar processors, pipelined processors, and multiprocessors David J. Lilja ; Pen-Chung Yew |
| title_short | Comparing parallelism extraction techniques |
| title_sort | comparing parallelism extraction techniques superscalar processors pipelined processors and multiprocessors |
| title_sub | superscalar processors, pipelined processors, and multiprocessors |
| topic | Multiprocessors Evaluation |
| topic_facet | Multiprocessors Evaluation |
| volume_link | (DE-604)BV008930033 |
| work_keys_str_mv | AT liljadavidj comparingparallelismextractiontechniquessuperscalarprocessorspipelinedprocessorsandmultiprocessors AT yewpenchung comparingparallelismextractiontechniquessuperscalarprocessorspipelinedprocessorsandmultiprocessors |