Euro ASIC '92: proceedings ; CNIT Paris, La Defénse ; June 1 - 5, 1992
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| Corporate Author: | |
|---|---|
| Format: | Conference Proceeding Book |
| Language: | English |
| Published: |
Los Alamitos, Calif., u.a.
IEEE Computer Soc. Press
1992
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| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Item Description: | Literaturangaben |
| Physical Description: | XII, 423 S. Ill., graph. Darst. |
| ISBN: | 0818628456 0818628464 0818628472 |
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MARC
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| 245 | 1 | 0 | |a Euro ASIC '92 |b proceedings ; CNIT Paris, La Defénse ; June 1 - 5, 1992 |
| 264 | 1 | |a Los Alamitos, Calif., u.a. |b IEEE Computer Soc. Press |c 1992 | |
| 300 | |a XII, 423 S. |b Ill., graph. Darst. | ||
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| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Literaturangaben | ||
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| 650 | 4 | |a Application specific integrated circuits |v Congresses | |
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| _version_ | 1820868125450567680 |
|---|---|
| adam_text |
Table
of Contents
Welcome
.
v
Local Organization Committee
.vi
Program Committee
.vi
Session
Al:
PGA Synthesis
Chair: W. Rosenstiel
ITEM: An If-Then-Else Minimizer for Logic Synthesis
.2
K. Karplus
Synthesis on Multiplexer-Based Programmable Devices Using (Ordered)
Binary Decision Diagrams
.8
T. Beeson, H. Bouzouzou, M. Crastes, and G. Saucier
FDD
Based
Technology
Mapping for FPGA
.14
E. Schubert, U. Kebschull, and W. Rosenstiel
Logic
Decomposition
for Programmable
Gate Arrays.
.19
T.
Ľuba,
M. Markowski, and B. Zbierzchowski
Automatic
Synthesis on
Table
Lookup-Based PGAs
.25
B.
Babba
and M. Crastes
Sequential Synthesis for
Table
Look Up
PGAs
.32
R. Murgai, R.K. Brayton, and A. Sangiovanni-Vincentelli
Session A2:
Register Transfer Level Synthesis
Chair:
L·
Claesen
Reduction of the Number of Symbolic Outputs of Finite State Machines
.40
G. Rietsche
Width Minimization of Field Encoded Outputs
.46
C.H. Chang and HJC Azzam
Interactive Register Transfer Level Synthesis Using Library Blocks
.53
A. Mignotte, M.-C.
Bertrand, M.
Crastes,
J.
Fron,
and
J. Rampon
High-Level Synthesis Applied to an ASIC Emulation Board
.59
N.
Wehn, H.J. Herpel, T.
Hollstein,
and M. Glesner
Session
A3:
Block Generator and Libraries
Chair:
G. Durand
ASIC Library Qualification: Criteria and Procedure
.66
K. Konishi, H. Takayoshi, K. Horikawa,
N.
Fudanuki, and E. Kawamoto
An Open Environment for Standard Cell and Gate Array Library Development
.72
ÄJV.Äoo
Extension of a Compilable Cell Library with Functionalities Concerning Numerical
Processing of Floating Point Data
.78
P. Grail, G. Mennecier, J.P.
Giocatone,
and C. Priol
Datapath Implementation: Bit-Slice Structure Versus Standard Cells
.83
12.
Leveugle,
C. Saftnia,
P.
Magarsnack,
and
L.
Sponga
An Open Characterization Component Tool
.89
J. Bonnardel and P. Raphalen
vn
Session A4: Design
Methodologies and Chip Architecture
Chair:
С.
Fleuteïot
A Sparse Data Scan Circuit for Pixel Detector Readout
.96
J.J. Jaeger,
С
Boutonnet, P.
Delpierre,
J. Waisbard, and F. Plisson
DSP ASIC Evaluation with Past Prototyping
.102
J. Isoaho, J. Pasanen, A. Nummefa, and H. Tenhunen
A Mixed Analog Digital Coprocessor for Image Scanning
.108
F. Pollet, B.
Ometti,
P.
Jespers,
and J.D.
Legat
Design of a CMOS ASIC Chip Featuring Analog Neural Computational Primitives.
. . 113
Ai. Vatte,
D.D.
Caviglia,
and CM. Bisio
Mobile Communication ASICs
.119
S. Morris
Session AS: Analog Design
Chair: E.
Schutz
Insensitive Current-Mode Biquad Implementation Based
Translinear
Current Conveyors
.126
A. Fabre and M.
Alami
A Schematic Driven Synthesis Tool for Analog Circuits
.131
B. Goffart, h. Menevaut, C. Meixenberger, and M. Degrauwe
A Wideband Current-Mode Amplifier Implemented from OTAs and ITS Applications
. . 135
A. Fabre and
N.
Mimeche
Telescopic Layout Cells for Analog CMOS Circuits
.139
S. Arlt, G. Scarbata, S.
Ritter,
and C.
Wisser
Session A6: Layout Synthesis, Standard Cell, Gate Array
Chair: J.C.Martin
Logic Synthesis for Automatic Layout
.146
P. Abouzeid, R. Leveugle, G. Saucier, and R. Jamier
Optimization Technique for Performance Driven Cell Generator
.152
N.
Azemard, V.
Bonzom,
S.
Ämat,
and
D.
Auvergne
Post-Placement Buffer Reoptimization
.156
D.
Brašen,
Г.
Schaefer, A. Ginetti, and
S. Chu
Session A7; Integrated Systems
Chair: M.Laurent
Wafer Scale System Integration Using Programmable Gate Array
.164
D.Bathia
Floorplanning with Power Routing
.165
D.R.
Brašen
An Algorithm for Standard-Cell and Gate Array Placement
.169
Z.V Apanovich and A.G. Marchuk
Session AS: Quality Test and Design for Test
Chair:
PJL
Menon
Quantifying Design Quality: A Model and Design Experiments
.172
E.J.
Aas,
К
Klingsheim.,
and
T.
Steen
Vlil
Integrating ASIC and Board Design-for-Testability
.178
M.
Kraak
A Modular Architecture for BIST of Boundary Scan Boards
.184
JMM.
Ferreira,
F.S.
Pinto, and
J.S.
Matos
ROTCO: A Reverse
Order Test Compaction Technique.
189
L.N.
Reddy,
I.
Pomerom,
and
SM.
Reddy
Session A9: Testability of Finite State Machine
Chair: S. Reddy
FSM-Based Test Generation Methods
—
A Survey
.196
P
JR. Menon
Design Methodology of FSMs with Intrinsic Fault Tolerance and
Recovery Capabilities
.201
R. Leveugle and L. Martinez
Functional Versus Random Test Generation for Controllers and
Finite State Machines
.207
M.
Karam
and G. Saucier
Session
AIO:
ASIC Design Methodologies
Chair: M.Bricaud
SETIPIC: Electrothermal Simulator for Power Integrated Circuits in
EDGE Environment
.214
L. Hebrard,
С
Klingelhofer, G. Jaquemod,
B. Boutherin, and M.
Le Helley
Basic Design Techniques for Both Low-Power and High-Speed ASICs
.220
С
Piguet, V.
Von Kaenel, J.M.
Masgonty,
J.-F.
Perotto,
and
R. Klootsema
Context-Based ASIC Synthesis
.226
S.H.
Kelem
and J.P.
Seidel
Creating a Nice-Looking Schematic from Its Netlist Description
.232
С
Nauts
Se88ÍonAll:
ASIC in Boards
Chair: A. Lorenzi
Specifying ASICs for Complex Mechatronic Systems
.238
P.
Solanti,
V. Paulasaari, J. Suutari, and H. Tenhunen
ASIC and Board Design of a High Performance Parallel Architecture
.244
A De
Gloria, P.
Foraboschi,
M.
Olivieri, and E. Guidetti
A Speller Board for Personal Computer
.250
M.J.
Calha
and
1С.
Teixeira
Session Cl: Architecture for Processors
Chair: G. Goto
A Single ASIC Device Completely Implements Control in an
80486-Based Personal Computer System
.258
J.J. Farrell HI
ASIC Design of a High-Performance RISC
.¿62
M.K Lee, B.Y. Choi, S.H. Lee, and KY. Lee
IX
Design
and Implementation of the Data-Path of a 32-bit
RISC Microprocessor: HRISCII
.
266
Y.I. El-Haffaf, A. Bouaraoua, and
A. Amari
A 64-Bit Floating Point Processing Unit for a RISC Microprocessor
.270
H. Kubosawa, A. Katsuno, H. Takahashi,
T. Sato,
A. Suga,
and G. Goto
Session C2: Image and Speech Processing, Video Circuits
Chair: J.L· Bouvresse
ASIC Design Using VLSI Technology CAD Tools: An Optimal Edge Detector Circuit
. . 276
N.
Zarka and M. Akil
Design of an Image Processing Integrated Circuit for Real Time Edge Detection
.280
M. Robert, J.P. Bonnaure, M. Paindavoine, and S. Hafdi
The U-VLC VLSI Implementation of a Universal Variable Length Coder
.284
L.
Descampa
and G.
Lizin
An ASIC Design for Linear Predictive Coding of Speech Signals
.288
J.-F. Wang, L.-Y. Liu, C.-H. Cheng, M.-H. Sheu,
Y.-L. Jeang, and J.-Y. Lee
Session C3: Image and Speech Processing, Video Circuits (Continued)
Chair: C.Pitot
A Transpose-Register for a 2D-FFT of
64x64
Pixel-Blocks
.294
H. Steckenbiller and K.
Holz
Real Time TV and HDTV Motion Estimation Chipset
.298
Cv.
Reventlow, M.
Talmi,
S.
Wolf,
M.
Ernst, and
К
Müller
An MPEG Decoder ASIC for Compact Disc Interactive
.301
С
Schepens
New VLSI ASIC Set for Digital TV Coding
.305
G. Lizin and S.
d'Agostino
Session C4: Educational Experiences and
Eurochip
Design
Chair: B.
Courtois
An Application Specific Microprocessor with Two-Level Built-in
Control Flow Checking Capabilities
.310
Г.
Michel,
К
Leveugle, F. Gaume, and R.
Roane
Single Chip Implementation of Real Time RNS IIR Digital Filters
.314
G.C. CardariUi,
R. Lojacono, M.
Salerno, and
F. Sargeni
Some Practical Experiences of Designing and Characterizing Full Custom Circuits
. . . 318
T. Rahkonen,
A Ruha,
R.
Rankinen,
T. Ruotsalainen,
E.
Raisanen-Ruotsalainen, and J. Kostamovaara
Student
Designs
of
MMICs
.322
B. Cabon,
N.
El Kamoun, and JX.
Carbonero
A
Four Channel, Input-Level-Tunable Data Acqusition Chip, Realized with an
Analog/Digital Array for Research and Education
.326
H. Acker, S. Schwehr, M. Hauck,
T. Persch, and J. Vollrath
Session
CS:
Industrial Applications
Chair: S.Brofferio
ASIC Chip Set for a Cycloconverter Drive
PCB
.332
E.B.
Patterson,
D. Morky,
CG. Oswald, and P.G. Holmes
Digital System
for a Static
Electric
Current
Meter.336
J.
Barbosa,
С.
Cruz,
P.
Nicolau,
C.
Pinto, and
I.
Teixeira
A Design Exercise of
a Micropower
Analog Digital ASIC Chip
.340
A. Ruha
and J. Kostamovaara
Session C6: DSP and Communication Circuits
Chair: R. Cottrell
A CMOS ASIC to Implement the TC Sublayer in the Physical Layer
of the ATM Network
.344
J.
Bulone
and M. Diaz
Nava
Application of Digital ECL and CMOS ASICs in Broadband ISDN Systems
.348
I.
Carretero
Pizzaro
CMOS Integrated Circuit for Ripple-Control Receiver
.352
J. Kučera
"SUPERCRYPT" ASIC Technology Facilitates a New Device Family for
Data Encryption
.356
K
-Н.
Mundt and H.
Eichel
MDRX: An ATM Building Block for Subscribers' Premises Networks
.360
L.
Dareis,
I.
Evers,
I.
Claes,
В.
De Ceulaer,
M.
Heylen, and J.-W. Weijers
Ping-Pong Supervisor for Synchronous Links
.364
P. Adde and
M. Jézequél
A Universal Hardware Architecture for Communication Networks
.368
R. Gerndt and J.
Kreyßig
Session C7: Dedicated Computation and Architecture
Chair:
M. Le Helley
COSIMA: A Self-Testable Simulated Annealing Processor for
Universal Cost Functions
.374
B. Eschermann, O. Haberl, O.
Bringmann,
and O. Seitz
A VLSI Chip Set for a Massively Parallel Scientific Processor
.378
J?. TripUxione
A High Performance Systolic Chip for Spelling Correction
.381
D. Lavenier
Session C8: Special Xilinx and Ac
tel
Prizes Sessions
Chairs: J. Schlageter and G. Wesley-Patterson
Design ofanH.261 Video Codec with
12
Xilinx LCAs
.386
AM. Praden, E.
Jouve, F.
Albert,
M. Dumas, and E. Siffredi
XILINX Circuit Gives Versatility and Size Reduction to Portable Electronic
Radio Frequency Tag Reader
.390
Alzad
Study and Implementation of a Real Time
3x3
Programmable Convolver with
Reconfigurable
Technology
.
392
M.
Alves
de Barros
and
M.
Akii
ASIC Integration of Bus Protocol for Distributed Industrial
Electromechanical System
.
396
V. Paulasaari, J. Suutari, P.
Solanti,
and H. Tenhunen
Implementation of a Crossbar Switch Buses Function in the A1280
FPGAfrom ACTEL
.400
L. Bathellier
Poster Session
ЗеашіопАІ
Experimental Results on the Impact of Factorization and Technology
Independent Mapping Option on Multilevel Synthesis
.402
P. Abouzeid, T. Besson, K. Sakouti, G. Saucier,
F. Gaume, and R.
Roane
Se$MÌonA3
Rad
Hard Silicon Compiler Library on SOI Technology
.404
I. Ckabert and D. Velhu
8e$eionA4
Pipelined TSPC Barrel Shifter with Scan Test Facilities for VLSI Implementation of
High Speed DSP Applications
.405
R.
Pereira,
JA.
Micheli,
and
J.M.
Solana
Seteion
A5
Using Standard-Cell Design Methodologies on a Gate-Array Base
.407
D.
Brašen,
J.
Shiflkr,
M.
Hartoog, and
S. Ashtaputre
Example of
CMOS Analog
Cells'
Automatic
Layouts: A Cascode Current Source
.409
H.
Mathias,
L.
Hébrard, G.
Jacquemod,
B.
Boutherin, and M. Le Helley
Operational
Amplifier
for Redundant Analog
Systems
.411
V. Ivanov
and V.
Ivanov
SewionAS
Localization of Faulty Operators on an ASIC by the Use of a Laser Beam
412
C.
Bouvet,
P.
Fouillât,
and J.P.
Dom
Modification of Logic on ASIC Devices
. 414
RNoone
Author Index
.
421
Xli |
| any_adam_object | 1 |
| author_corporate | Euro ASIC Paris |
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| author_facet | Euro ASIC Paris |
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| classification_rvk | SS 1992 |
| classification_tum | ELT 360f |
| ctrlnum | (OCoLC)26082418 (DE-599)BVBBV008229823 |
| discipline | Elektrotechnik |
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| genre | (DE-588)1071861417 Konferenzschrift 1992 Paris gnd-content |
| genre_facet | Konferenzschrift 1992 Paris |
| id | DE-604.BV008229823 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T13:19:24Z |
| institution | BVB |
| institution_GND | (DE-588)5102884-0 |
| isbn | 0818628456 0818628464 0818628472 |
| language | English |
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| physical | XII, 423 S. Ill., graph. Darst. |
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| spelling | Euro ASIC 1992 Paris Verfasser (DE-588)5102884-0 aut Euro ASIC '92 proceedings ; CNIT Paris, La Defénse ; June 1 - 5, 1992 Los Alamitos, Calif., u.a. IEEE Computer Soc. Press 1992 XII, 423 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Literaturangaben Circuitos integrados larpcal Application specific integrated circuits Congresses Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1992 Paris gnd-content Kundenspezifische Schaltung (DE-588)4122250-7 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005431729&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Euro ASIC '92 proceedings ; CNIT Paris, La Defénse ; June 1 - 5, 1992 Circuitos integrados larpcal Application specific integrated circuits Congresses Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| subject_GND | (DE-588)4122250-7 (DE-588)1071861417 |
| title | Euro ASIC '92 proceedings ; CNIT Paris, La Defénse ; June 1 - 5, 1992 |
| title_auth | Euro ASIC '92 proceedings ; CNIT Paris, La Defénse ; June 1 - 5, 1992 |
| title_exact_search | Euro ASIC '92 proceedings ; CNIT Paris, La Defénse ; June 1 - 5, 1992 |
| title_full | Euro ASIC '92 proceedings ; CNIT Paris, La Defénse ; June 1 - 5, 1992 |
| title_fullStr | Euro ASIC '92 proceedings ; CNIT Paris, La Defénse ; June 1 - 5, 1992 |
| title_full_unstemmed | Euro ASIC '92 proceedings ; CNIT Paris, La Defénse ; June 1 - 5, 1992 |
| title_short | Euro ASIC '92 |
| title_sort | euro asic 92 proceedings cnit paris la defense june 1 5 1992 |
| title_sub | proceedings ; CNIT Paris, La Defénse ; June 1 - 5, 1992 |
| topic | Circuitos integrados larpcal Application specific integrated circuits Congresses Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| topic_facet | Circuitos integrados Application specific integrated circuits Congresses Kundenspezifische Schaltung Konferenzschrift 1992 Paris |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005431729&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT euroasicparis euroasic92proceedingscnitparisladefensejune151992 |