Proceedings: May 27 - 29, 192, Sendai, Japan
Saved in:
| Corporate Author: | |
|---|---|
| Format: | Conference Proceeding Book |
| Language: | English |
| Published: |
Los Alamitos, Calif.
IEEE Computer Soc. Press
1992
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| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XV, 482 S. Ill., graph. Darst. |
| ISBN: | 0818626801 0818626828 081862681X |
Staff View
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| 111 | 2 | |a International Symposium on Multiple Valued Logic |n 22 |d 1992 |c Sendai |j Verfasser |0 (DE-588)5083253-0 |4 aut | |
| 245 | 1 | 0 | |a Proceedings |b May 27 - 29, 192, Sendai, Japan |c the twenty-second International Symposium on Multiple-Valued Logic |
| 264 | 1 | |a Los Alamitos, Calif. |b IEEE Computer Soc. Press |c 1992 | |
| 300 | |a XV, 482 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 7 | |a Commutation, Théorie de la - Congrès |2 ram | |
| 650 | 7 | |a Hardware |2 swd | |
| 650 | 7 | |a Logique multivalente - Congrès |2 ram | |
| 650 | 7 | |a Theoretische Informatik |2 swd | |
| 650 | 7 | |a VLSI |2 inriac | |
| 650 | 7 | |a algèbre |2 inriac | |
| 650 | 7 | |a complétude |2 inriac | |
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| 650 | 7 | |a conception logique |2 inriac | |
| 650 | 7 | |a fiabilité système |2 inriac | |
| 650 | 7 | |a logique floue |2 inriac | |
| 650 | 7 | |a logique plurivalente |2 inriac | |
| 650 | 7 | |a minimisation |2 inriac | |
| 650 | 7 | |a réseau neuronal |2 inriac | |
| 650 | 7 | |a test |2 inriac | |
| 650 | 4 | |a Many-valued logic |v Congresses | |
| 650 | 4 | |a Switching theory |v Congresses | |
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| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 1993 |z Sendai |2 gnd-content | |
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| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-005283014 | |
Record in the Search Index
| _version_ | 1820868125140189184 |
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| adam_text |
Table
of Contents
Symposium Chair's Message
.
v
Program Chair's Message
.vi
Executive Committee
.
.vii
Program Committee
.
vii
Financial Committee
.
vii
Publicity and Publications Committee
.viii
Local Arrangements Committee
.viii
Organizing Committee
.ix
Referees
.
χ
SessionI: Invited Address
High-Speed Digital Circuits for
a Josephson
Computer
.2
S. Hasuo
Session Ha: Device-Based Circuit
A Superconducting Ternary Systolic Array Processor
.10
M. Morisue and F.-Q. Li
Heterojunction Bipolar Technology for Emitter-Coupled Multiple-Valued Logic in
Gigahertz Adders and Multipliers
.18
LJ. Micheel
Unique Folding and Hysteresis Characteristics of
RTD
for
Multi-
Valued Logic and
Counting Applications
.27
S.-J. Wei and H.C.Lin
Session IIb: Test
Easily Testable Multiple-Valued Cellular Arrays
.36
N.
Kamiura, Y.
Hata,
F.
Miyawaki, and K. Yamato
Aliasing in Multiple-Valued Test Data Compaction
.43
G. Edirisooriya and
J T
.
Robinson
A New Balanced Gate for Structural Testing
.51
H.M. Razavi andP.W. Wong
Session HI a
:
Logic
Minimiza
tion
Direct Cover MVL Minimization with Cost-Tables
.58
G.W.Dueck
Multiple-Valued Programmable Logic Array Minimization by Simulated Annealing
.66
G.W. Dueck, R.C. Earle, P. Tirumalai, andJ.T. Butler
Experiences of Parallel Processing with Direct Cover Algorithms for
Multiple-Valued Logic Minimization
.75
С
Yang and
0.
Oral
Session IIIb: Neural Network
Design of a 4-Valued Digital Multiplier Using an Artificial Heterogeneous
Two-Layered Neural Network
.84
C.-LJ.
Ни
Layered MVL Neural Networks Capable of Recognizing Translated Characters
.88
T. Watanabe and M. Matsumolo
A Deductive Neural-Logic System
.96
J.-H. Urn, H.-C.
Lui,
and
H.-H.
Teh
Session
W
a: Circuit Design
Towards the Realization of ^Valued CMOS Circuits
.104
K. LeiandZ.G. Vranesic
Incremental Gate: A Method to Compute Minimal Cost
CCD
Realizations of MVL Functions
. . . .111
MM. Abd-El-Barr and H. Choy
The Theory of Clipping Voltage-Switches and Design of Quaternary nMOS Circuits
.119
X.Wu
Session IVb: Algebra I
An Application of the p-Valued Input, q-Kind-Valued Output Logic to the Synthesis of the
p-Valued Logical Networks
.128
T. Haga
On the Efficient Decoding of Reed-Solomon Codes Based on GMD Criterion
.138
K.
Araki,
M.
Takada,
and
M.
Morii
Defaults as First-Class Citizens
.146
P. Doherty and
W. Łukasiewicz
Session V: Invited Address
On the Performance of Multivalued Integrated Circuits: Past, Present and Future
.156
D. Etiemble
Session VIa: Reliable Systems
Concurrent Checking and Unidirectional Errors in Multiple-Valued Circuits
.166
D. Wessels andJ.C. Muxio
Application of Fail-Safe Multiple-Valued Logic to Control of Power Press
.174
M. Sakai, M.
Kato,
К.
Futsuhara, and M.
Mukaidono
Fault Analysis on Two-Level (K+l)-Valued Logic Circuits
.181
HM. Wang, CL. Lee, and
JE.
Chen
Session VIb: Algebra
Π
(n+l)-Valued Modal Implicative Semilattices
.190
M .C.
Canals
Frau
and A.V. Figallo
Multiplicative Bases Approach in Multiplevalued Threshold Logic
.197
SX.
Blyumin
Fuzzifying Topological Groups Based on Completely Distributive Residuated
Lattice-Valued Logic (I)
. _
19g
J.Shen
Session VIIa: Current Mode Circuits
Dynamic Current-Mode Multi-Valued
MOS
Memory with Error Correction
. 208
EX
J
.
Lee and P.
G
.
Gúlák
Bi-CMOS Current Mode Multiple Valued Logic Circuits with 1.5V Supply Voltage
.216
K.Taniguchi.M. Sasaki. Y. Ogata, F.Ueno, and
T. ¡noue
On the Synthesis of MVL Functions for Current-Mode CMOS Circuits Implementation
.221
MB. Abd-El-Barr and M. I. Mahroos
A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter Circuit
.229
K.W. Current
Session VIIb: Algebra III
On Multiple-Valued Logic Functions
Monotonie
with Respect to Ambiguity
.236
K. Nakashima and
N.
Takagi
Fundamental Properties of Extended Kleene-Stone Logic Functions
.243
N.
Takagi, K. Nakashima, and M. Mukaidono
On Set-Valued Functions and Boolean Collections
.250
R. Tosic, I. Stojmenovic, DA. Simovici, and
С
Reischer
Rectangular Algebras
.255
R.
Pöschel
and
M.
Reichet
Session
VIII:
Invited Address
A Universal Logic Machine
.262
MA. Perkowski
Session IXa: VLSI I
Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for
Real-Time
Rule-Based Systems
.274
T. Hanyu, K. Takeda, and T. Higuchi
Set-Valued Logic Networks Based on Optical Wavelength Multiplexing
.282
S. Maeda, T. Aoki, and T. Higuchi
Area-Efficient Implication Circuits for Very Dense
Łukasiewicz
Logic Arrays
.291
J.W. Mills
SessionIXb: Completeness
Semirigid Sets of Central Relations Over a Finite Domain
.300
M. Miyakawa, A. Nozaki, G. Pogosyan, and I.G
.
Rosenberg
Amplification of the Functional Closure Operation
.308
V.Lashkia
The Completeness Problem on the Product of Algebras of Finite Valued Logic
.312
BA.Romov
Session X: Invited Address
A Completeness Criterion for
Semi-Affine
Algebras
.314
Á.
Szendrei
SessionXIa: VLSI II
Design of a Multiple-Valued VLSI Processor for Digital Control
.322
K. Shimabukuro, M. Kameyama, and T. Higuchi
Residue Arithmetic Based Multiple-Valued VLSI Image Processor
.330
M. Honda, M. Kameyama, and T. Higuchi
Parallel Hardware Algorithms with Redundant Number Representations for
Multiple-Valued Arithmetic VLSI
.337
S. Kawahito, Y.
Mistui,
M.
¡snida,
and
T. Nakamura
Session
ХІв:
Spectral Techniques
Binary Input/Ternary Output Switching Circuits Designed Via the Sign Transformation
.348
P. Besslich and
E
A.
Trachtenberg
Autocorrelation Techniques for Multi-Bit Decoder PLAs
.355
R. TomczukandDM. Miller
Some Remarks on Fourier Transform and Differential Operators for Digital Functions
.365
R.S. Stankovic
Session
XII:
Special Session
Profiles of Topics and Authors of the International Symposium on
Multiple-Valued Logic for
1971-1991.372
S.W.
Butler and J.T. Butler
Session XIIIa: Logic Design
Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinational Circuits
.382
5.
Tamaia, M. Kameyama, and T. Higuchi
Optimal Output Assignment and the Maximum Number of
Implicante
Needed to Cover the
Multiple-Valued Logic Functions
.389
ľ.
Hata,
F.
Miyawaki, and
К.
Yamato
On the Use of Multiple-Valued Switch-Level Algebra to Analyze Binary
MOS
Bridge
Circuits and Dynamic Circuits
.396
M.
Ни,
S.
Хи,
and
K.C.
Smith
Fast Logic Synthesis Based Upon Ternary Universal Logic Module Us
.401
B.
Fei
and
N.
Zhuang
Session XIIIb: Fuzzy Logic I
An Automatic Adjustment Method of Backpropagation Learning Parameters,
Using Fuzzy Inference
.410
F.
Veno,
T.
Inoue,
B.-U.-H.
Baloch,
and
T. Yamamoto
A Meaningful Infinite-Valued Switching Function
—
Fuzzy Threshold Function and Its
Application to Process Control
.415
Y. Yamamoto
Inverted Pendulum Controlled Circuit Using Fuzzy State Memory with Voltage Mode
Fuzzy State Memory
.423
Y. Shirai, F.
Veno,
T.
Inoue,
M.
Inoue, and
К.
Tasaki
A Proposal of Fault-Checking Fuzzy Control
.428
H.
Ito,
T.
Matsubara,
T.
Kurokawa, and Y.
Koga
Session
XIV
a: EXOR logic
Efficient Derivation of Reed-Muller Expansions in Multiple-Valued Logic Systems
.436
ß.
Harking and C.
Moraga
The Generalized
Orthonormal
Expansion of Functions with Multiple-Valued Inputs and
Some of Its Applications
.442
MA. Perkowslci
Optimization of Multiple-Valued AND-EXOR Expressions Using
Multiple-Place Decision Diagrams
.,451
T. Sasao
XIV
Session XIVb: Fuzzy Logic II
On a Logic Based on Fuzzy Modalities
.460
A.Nakamura
Revision Principle for Approximate Reasoning-Based on Semantic Revising Method
.467
Z. Shen, L. Ding,
H.C.
Lui,
P.
-Z.
Wang, and M. Mukaidono
On Yager's Aggregation Operators
.474
HJ. Skala
Session XV: Invited Address
Fuzzy Logic and the Calculus of Fuzzy If-Then Rules
.480
LA. Zadeh
Author Index
.481
XV |
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| discipline | Informatik Mathematik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 1993 Sendai gnd-content |
| genre_facet | Konferenzschrift 1993 Sendai |
| id | DE-604.BV008028782 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T13:19:23Z |
| institution | BVB |
| institution_GND | (DE-588)5083253-0 |
| isbn | 0818626801 0818626828 081862681X |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-005283014 |
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| physical | XV, 482 S. Ill., graph. Darst. |
| publishDate | 1992 |
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| publisher | IEEE Computer Soc. Press |
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| spelling | International Symposium on Multiple Valued Logic 22 1992 Sendai Verfasser (DE-588)5083253-0 aut Proceedings May 27 - 29, 192, Sendai, Japan the twenty-second International Symposium on Multiple-Valued Logic Los Alamitos, Calif. IEEE Computer Soc. Press 1992 XV, 482 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Commutation, Théorie de la - Congrès ram Hardware swd Logique multivalente - Congrès ram Theoretische Informatik swd VLSI inriac algèbre inriac complétude inriac conception circuit inriac conception logique inriac fiabilité système inriac logique floue inriac logique plurivalente inriac minimisation inriac réseau neuronal inriac test inriac Many-valued logic Congresses Switching theory Congresses Mehrwertige Logik (DE-588)4169335-8 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1993 Sendai gnd-content Mehrwertige Logik (DE-588)4169335-8 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005283014&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings May 27 - 29, 192, Sendai, Japan Commutation, Théorie de la - Congrès ram Hardware swd Logique multivalente - Congrès ram Theoretische Informatik swd VLSI inriac algèbre inriac complétude inriac conception circuit inriac conception logique inriac fiabilité système inriac logique floue inriac logique plurivalente inriac minimisation inriac réseau neuronal inriac test inriac Many-valued logic Congresses Switching theory Congresses Mehrwertige Logik (DE-588)4169335-8 gnd |
| subject_GND | (DE-588)4169335-8 (DE-588)1071861417 |
| title | Proceedings May 27 - 29, 192, Sendai, Japan |
| title_auth | Proceedings May 27 - 29, 192, Sendai, Japan |
| title_exact_search | Proceedings May 27 - 29, 192, Sendai, Japan |
| title_full | Proceedings May 27 - 29, 192, Sendai, Japan the twenty-second International Symposium on Multiple-Valued Logic |
| title_fullStr | Proceedings May 27 - 29, 192, Sendai, Japan the twenty-second International Symposium on Multiple-Valued Logic |
| title_full_unstemmed | Proceedings May 27 - 29, 192, Sendai, Japan the twenty-second International Symposium on Multiple-Valued Logic |
| title_short | Proceedings |
| title_sort | proceedings may 27 29 192 sendai japan |
| title_sub | May 27 - 29, 192, Sendai, Japan |
| topic | Commutation, Théorie de la - Congrès ram Hardware swd Logique multivalente - Congrès ram Theoretische Informatik swd VLSI inriac algèbre inriac complétude inriac conception circuit inriac conception logique inriac fiabilité système inriac logique floue inriac logique plurivalente inriac minimisation inriac réseau neuronal inriac test inriac Many-valued logic Congresses Switching theory Congresses Mehrwertige Logik (DE-588)4169335-8 gnd |
| topic_facet | Commutation, Théorie de la - Congrès Hardware Logique multivalente - Congrès Theoretische Informatik VLSI algèbre complétude conception circuit conception logique fiabilité système logique floue logique plurivalente minimisation réseau neuronal test Many-valued logic Congresses Switching theory Congresses Mehrwertige Logik Konferenzschrift 1993 Sendai |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005283014&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT internationalsymposiumonmultiplevaluedlogicsendai proceedingsmay2729192sendaijapan |