MOS ICs: from Basics to ASICs
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Weinheim [u.a.]
VCH
1992
|
| Edition: | 1. ed. |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Item Description: | Aus. d. dt. übers. |
| Physical Description: | XXIX, 430 S. Ill., graph. Darst. |
| ISBN: | 3527283889 1560811978 |
Staff View
MARC
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| 100 | 1 | |a Veendrick, Harry J. M. |e Verfasser |4 aut | |
| 240 | 1 | 0 | |a MOS ICs |
| 245 | 1 | 0 | |a MOS ICs |b from Basics to ASICs |c H. J. M. Veendrick |
| 250 | |a 1. ed. | ||
| 264 | 1 | |a Weinheim [u.a.] |b VCH |c 1992 | |
| 300 | |a XXIX, 430 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Aus. d. dt. übers. | ||
| 650 | 4 | |a Engineering (Electronic) | |
| 650 | 4 | |a Integrated circuits | |
| 650 | 4 | |a Metal oxide semiconductors | |
| 650 | 4 | |a Application specific integrated circuits | |
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Record in the Search Index
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CONTENTS
FOREWORD V
PREFACE VI
OVERVIEW O
F
SYMBOLS XVII
LIST O
F
PHYSICAL CONSTANTS XXI
CONTENTS XXIII
1 BASIC PRINCIPLES 1
1.1 INTRODUCTION 1
1.2 THE FIELD-EFFECT PRINCIPLE 2
1.3 THE INVERSION-LAYER MOS-TRANSISTOR 5
1.3.1 THE METAL-OXIDE-SEMICONDUCTOR (MOS) CAPACITOR 11
1.3.2 THE INVERSION-LAYER MOS TRANSISTOR 15
1.4 DERIVATION OF SIMPLE MOS FORMULAS 24
1.5 THE BACK-BIAS EFFECT
(BACK-GATE EFFECT, BODY EFFECT) 28
1.6 FACTORS WHICH CHARACTERISE THE BEHAVIOUR OF THE MOS TRAN
SISTOR 32
1.7 DIFFERENT TYPES OF MOS TRANSISTORS 33
1.8 PARASITIC MOS TRANSISTORS 35
1.9 MOS TRANSISTOR SYMBOLS 37
1.10 CAPACITANCES IN MOS STRUCTURES 39
1.11 CONCLUSIONS 50
1.12 REFERENCES 51
1.13 EXERCISES 52
XXIII
HTTP://D-NB.INFO/921292880
2 PHYSICAL AND GEOMETRICAL EFFECTS ON THE BEHAVIOUR O
F
T
H
E
MOS TRANSISTOR 57
2.1 INTRODUCTION 57
2.2 TEMPERATURE EFFECTS 58
2.3 CARRIER-MOBILITY DEGRADATION 59
2.4 CHANNEL-LENGTH MODULATION AND
STATIC-DRAIN FEEDBACK 62
2.4.1 CHANNEL-LENGTH MODULATION 62
2.4.2 STATIC-DRAIN FEEDBACK
(DRAIN-INDUCED BARRIER LOWERING) 65
2.5 SMALL-CHANNEL EFFECTS 66
2.5.1 SHORT-CHANNEL EFFECT 66
2.5.2 NARROW-CHANNEL EFFECT 68
2.5.3 MODELLING OF SMALL-CHANNEL EFFECTS 69
2.6 PUNCH-THROUGH 71
2.7 HOT-CARRIER EFFECT 72
2.7.1 INTRODUCTION 72
2.7.2 THE ELECTRIC FIELD IN MOS TRANSISTORS 72
2.7.3 IMPACT IONIZATION 74
2.7.4 HOT-CARRIER DEGRADATION 75
2.7.5 REDUCING THE MAXIMUM ELECTRIC FIELD IN A MOS
TRANSISTOR 78
2.8 WEAK-INVERSION BEHAVIOUR OF THE MOS
TRANSISTOR 82
2.9 CONCLUSIONS 84
2.10 REFERENCES 85
2.11 EXERCISES 87
3 FABRICATION O
F
MOS DEVICES 89
3.1 INTRODUCTION 89
3.2 PHOTOLITHOGRAPHY IN MOS PROCESSES 91
3.3 ETCHING 97
3.4 OXIDATION 98
3.5 DEPOSITION 100
3.6 DIFFUSION AND ION IMPLANTATION 102
3.7 BASIC MOS TECHNOLOGIES 104
3.7.1 THE BASIC SILICON-GATE NMOS PROCESS 104
3.7.2 THE BASIC COMPLEMENTARY MOS (CMOS) PROCESS . 107
3.7.3 TYPES OF CMOS PROCESSES 114
3.8 TESTING, YIELD AND PACKAGING 120
XXIV
3.8.1 TESTING 120
3.8.2 YIELD 124
3.8.3 PACKAGING 129
3.9 QUALITY AND RELIABILITY 140
3.9.1 QUALITY 140
3.9.2 RELIABILITY 140
3.10 CONCLUSIONS 142
3.11 REFERENCES 143
3.12 EXERCISES 145
4 NMOS CIRCUITS 147
4.1 INTRODUCTION 147
4.2 ELECTRICAL DESIGN OF NMOS CIRCUITS 148
4.2.1 INTRODUCTION 148
4.2.2 THE DC BEHAVIOUR 149
4.2.3 THE TRANSIENT RESPONSE 158
4.2.4 TRANSFORMING A LOGIC FUNCTION INTO AN NMOS TRAN
SISTOR CIRCUIT 171
4.2.5 SUMMARY OF ELECTRICAL DESIGN RULES 174
4.3 DIGITAL NMOS CIRCUITS 176
4.3.1 INTRODUCTION 176
4.3.2 STATIC NMOS CIRCUITS 177
4.3.3 DYNAMIC NMOS CIRCUITS 182
4.4 INPUT AND OUTPUT CIRCUITS (BUFFERS) 192
4.5 LAYOUT-DESIGN OF NMOS CIRCUITS 196
4.5.1 INTRODUCTION 196
4.5.2 LAYOUT DESIGN RULES 196
4.5.3 THE 'STICK' DIAGRAM 202
4.5.4 GUIDELINES FOR LAYOUT DESIGN 205
4.6 CONCLUSIONS 207
4.7 REFERENCES 208
4.8 EXERCISES 209
5 CMOS CIRCUITS 213
5.1 INTRODUCTION 213
5.2 ELECTRICAL DESIGN OF CMOS CIRCUITS 215
5.2.1 INTRODUCTION 215
5.2.2 THE CMOS INVERTER 216
5.2.3 LATCH-UP 232
5.2.4 POINTS TO NOTE 235
XXV
5.3 DIGITAL CMOS CIRCUITS 237
5.3.1 INTRODUCTION 237
5.3.2 STATIC CMOS CIRCUITS 237
5.3.3 CLOCKED CMOS CIRCUITS 243
5.3.4 DYNAMIC CMOS CIRCUITS 247
5.3.5 OTHER TYPES OF CMOS CIRCUITRY 251
5.3.6 CHOOSING A CMOS IMPLEMENTATION 252
5.3.7 CLOCKING STRATEGIES 253
5.4 CMOS INPUT, OUTPUT (I/O) AND
PROTECTION CIRCUITS 254
5.4.1 CMOS INPUT CIRCUITS 254
5.4.2 CMOS OUTPUT BUFFERS (DRIVERS) 255
5.4.3 MOS IC PROTECTION CIRCUITS 257
5.5 LAYOUT DESIGN OF CMOS CIRCUITS 264
5.6 CONCLUSIONS 271
5.7 REFERENCES 272
5.8 EXERCISES 274
6 SPECIAL CIRCUITS, DEVICES AND TECHNOLOGIES 277
6.1 INTRODUCTION 277
6.2 CHARGE-COUPLED DEVICES (CCDS) 278
6.2.1 INTRODUCTION 278
6.2.2 BASIC SCCD OPERATION 278
6.2.3 BURIED-CHANNEL CCDS (BCCDS) 282
6.2.4 COMPARISON OF BCCDS AND SCCDS 283
6.2.5 APPLICATIONS 283
6.3 POWER MOSFET TRANSISTORS 285
6.3.1 INTRODUCTION 285
6.3.2 TECHNOLOGY AND OPERATION 287
6.3.3 APPLICATIONS 288
6.4 BICMOS DIGITAL CIRCUITS 289
6.4.1 INTRODUCTION 289
6.4.2 BICMOS TECHNOLOGY 289
6.4.3 BICMOS CHARACTERISTICS 291
6.4.4 BICMOS CIRCUIT PERFORMANCE 292
6.4.5 FUTURE EXPECTATIONS AND MARKET TRENDS 295
6.5 CONCLUSIONS 296
6.6 REFERENCES 297
6.7 EXERCISES 299
XXVI
7 MEMORIES 301
7.1 INTRODUCTION 301
7.2 SERIAL MEMORIES 305
7.3 RANDOM-ACCESS MEMORIES (RAM) 306
7.3.1 INTRODUCTION 306
7.3.2 STATIC RAMS (SRAM) 306
7.3.3 DYNAMIC RAMS (DRAM) 314
7.3.4 ERROR SENSITIVITY 319
7.3.5 REDUNDANCY 319
7.4 READ-ONLY MEMORIES (ROM) 320
7.4.1 INTRODUCTION 320
7.4.2 ROM MEMORY ELEMENTS 320
7.5 PROGRAMMABLE READ-ONLY MEMORIES 324
7.5.1 INTRODUCTION 324
7.5.2 PROMS (PROGRAMMABLE READ-ONLY MEMORIES) . . . 324
7.5.3 EPROMS (ERASABLE PROMS) 324
7.5.4 EEPROMS (ELECTRICALLY ERASABLE PROMS) 325
7.5.5 NVRAM (NON-VOLATILE RAM) 327
7.5.6 BRAM (BATTERY RAM) 328
7.5.7 CLASSIFICATION OF THE VARIOUS MEMORIES 328
7.6 CONCLUSIONS 330
7.7 REFERENCES 331
7.8 EXERCISES 332
8 VERY LARGE SCALE INTEGRATION (VLSI) 335
8.1 INTRODUCTION 335
8.2 ABSTRACTION LEVELS FOR VLSI 337
8.2.1 INTRODUCTION 337
8.2.2 SYSTEM LEVEL 338
8.2.3 FUNCTIONAL LEVEL 339
8.2.4 RTL LEVEL 340
8.2.5 LOGIC-FUNCTION LEVEL 343
8.2.6 LOGIC-GATE LEVEL 343
8.2.7 TRANSISTOR LEVEL 344
8.2.8 LAYOUT LEVEL 344
8.2.9 CONCLUSIONS 345
8.3 CAD TOOLS FOR SYNTHESIS AND VERIFICATION 348
8.3.1 INTRODUCTION 348
8.3.2 SYSTEM-LEVEL CAD TOOLS 349
8.3.3 FUNCTIONAL-LEVEL CAD TOOLS 349
XXVII
8.3.4 RTL-LEVEL CAD TOOLS 349
8.3.5 LOGIC-FUNCTION LEVEL CAD TOOLS 349
8.3.6 LOGIC-GATE LEVEL CAD TOOLS 350
8.3.7 TRANSISTOR-LEVEL CAD TOOLS 350
8.3.8 TIMING VERIFICATION 352
8.3.9 HYBRID SIMULATION 353
8.4 CAD TOOLS FOR LAYOUT 354
8.4.1 INTRODUCTION 354
8.4.2 CONVENTIONAL GATE-ARRAY LAYOUT IMPLEMENTATION . . 356
8.4.3 STANDARD-CELL LAYOUT IMPLEMENTATION 360
8.4.4 ROM AND PLA LAYOUT IMPLEMENTATIONS 361
8.4.5 BIT-SLICE LAYOUT IMPLEMENTATION 364
8.4.6 HIERARCHICAL LAYOUT IMPLEMENTATION 365
8.4.7 HAND-CRAFTED LAYOUT IMPLEMENTATION 367
8.4.8 MEMORY LAYOUT IMPLEMENTATION 368
8.4.9 THE CHOICE OF A LAYOUT IMPLEMENTATION FORM .
.
.
.
370
8.5 CONCLUSIONS 373
8.6 REFERENCES 375
8.7 EXERCISES 376
9 ASICS 377
9.1 INTRODUCTION 377
9.2 CUSTOMER MOTIVATION FOR THE USE OF ASICS 379
9.3 DIGITAL ASICS 381
9.4 TRENDS IN THE DIGITAL-CMOS ASIC
MARKET 384
9.4.1 THE EPLD MARKET 385
9.4.2 THE GATE-ARRAY MARKET 386
9.4.3 THE CELL-BASED CUSTOM-DESIGN MARKET 387
9.4.4 CONCLUSIONS 387
9.5 TECHNOLOGICAL DEVELOPMENTS 389
9.5.1 INTRODUCTION 389
9.5.2 GENERAL ASIC DEVELOPMENTS 389
9.5.3 TECHNOLOGICAL DEVELOPMENTS IN THE CELL-BASED
DIGITAL-CMOS ASIC SECTOR 390
9.5.4 TECHNOLOGICAL DEVELOPMENTS IN THE GATE-ARRAY
DIGITAL-CMOS ASIC SECTOR 391
9.5.5 TECHNOLOGICAL DEVELOPMENTS IN THE PLD
DIGITAL-CMOS ASIC SECTOR 395
9.5.6 SPECIAL APPROACHES FOR FAST PROTOTYPING 397
XXVIII
9.6 POTENTIAL ASIC DESIGN PROBLEMS 399
9.7 CONCLUSIONS 400
9.8 REFERENCES 401
9.9 EXERCISES 402
10 EFFECTS O
F
SCALING O
N
MOS TRANSISTORS AND M
O
S ICS 405
10.1 INTRODUCTION 405
10.2 SCALING EFFECTS ON MOS TRANSISTOR PARAMETERS AND CIRCUIT
PERFORMANCE 406
10.3 CONSEQUENCES OF INCREASED POWER DENSITY DUE TO SCALING . 409
10.4 CONCLUSIONS 414
10.5 REFERENCES 416
10.6 EXERCISES 417
INDEX 418
XXIX |
| any_adam_object | 1 |
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| author_facet | Veendrick, Harry J. M. |
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| id | DE-604.BV007731754 |
| illustrated | Illustrated |
| indexdate | 2024-12-02T09:04:42Z |
| institution | BVB |
| isbn | 3527283889 1560811978 |
| language | English |
| lccn | 92036753 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-005081819 |
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| owner_facet | DE-355 DE-BY-UBR DE-29T DE-384 DE-83 DE-634 DE-11 |
| physical | XXIX, 430 S. Ill., graph. Darst. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| publisher | VCH |
| record_format | marc |
| spelling | Veendrick, Harry J. M. Verfasser aut MOS ICs MOS ICs from Basics to ASICs H. J. M. Veendrick 1. ed. Weinheim [u.a.] VCH 1992 XXIX, 430 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Aus. d. dt. übers. Engineering (Electronic) Integrated circuits Metal oxide semiconductors Application specific integrated circuits MOS (DE-588)4130209-6 gnd rswk-swf MOS-Schaltung (DE-588)4135571-4 gnd rswk-swf MOS (DE-588)4130209-6 s DE-604 MOS-Schaltung (DE-588)4135571-4 s DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005081819&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Veendrick, Harry J. M. MOS ICs from Basics to ASICs Engineering (Electronic) Integrated circuits Metal oxide semiconductors Application specific integrated circuits MOS (DE-588)4130209-6 gnd MOS-Schaltung (DE-588)4135571-4 gnd |
| subject_GND | (DE-588)4130209-6 (DE-588)4135571-4 |
| title | MOS ICs from Basics to ASICs |
| title_alt | MOS ICs |
| title_auth | MOS ICs from Basics to ASICs |
| title_exact_search | MOS ICs from Basics to ASICs |
| title_full | MOS ICs from Basics to ASICs H. J. M. Veendrick |
| title_fullStr | MOS ICs from Basics to ASICs H. J. M. Veendrick |
| title_full_unstemmed | MOS ICs from Basics to ASICs H. J. M. Veendrick |
| title_short | MOS ICs |
| title_sort | mos ics from basics to asics |
| title_sub | from Basics to ASICs |
| topic | Engineering (Electronic) Integrated circuits Metal oxide semiconductors Application specific integrated circuits MOS (DE-588)4130209-6 gnd MOS-Schaltung (DE-588)4135571-4 gnd |
| topic_facet | Engineering (Electronic) Integrated circuits Metal oxide semiconductors Application specific integrated circuits MOS MOS-Schaltung |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005081819&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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