Formal methods for VLSI design:
Saved in:
| Format: | Conference Proceeding Book |
|---|---|
| Language: | English |
| Published: |
Amsterdam u.a.
North-Holland
1990
|
| Series: | IFIP WG 10 5 lecture notes
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Item Description: | Literaturangaben |
| Physical Description: | 329 S. graph. Darst. |
| ISBN: | 0444888586 |
Staff View
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| 245 | 1 | 0 | |a Formal methods for VLSI design |c ed. by Jørgen Staunstrup |
| 264 | 1 | |a Amsterdam u.a. |b North-Holland |c 1990 | |
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| 336 | |b txt |2 rdacontent | ||
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| 490 | 0 | |a IFIP WG 10 5 lecture notes | |
| 500 | |a Literaturangaben | ||
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Record in the Search Index
| _version_ | 1820868136602173440 |
|---|---|
| adam_text |
Contents
Circuit
design
in
Ruby
13
1.1
Introduction
. 13
1.1.1
The shape of this chapter
. 14
1.1.2
The
rôle
of pictures
. 15
1.2
Composition and inverse
. 16
1.2.1
Repeated composition
. 17
1.2.2
Inverse
. 17
1.2.3
Identity and types
. 18
1.2.4
Conjugation
. 19
1.3
Lists and tuples
. 20
1.3.1
Parallel composition
. 20
1.3.2
Pairs and projections
. 21
1.3.3
Types for lists
. 21
1.3.4
Map
. 23
1.3.5
Reverse
. 24
1.3.6
Triangle
. 25
1.4
Rows and columns
. 26
1.4.1
Beside and below
. 26
1.4.2
Reflections
. 29
1.4.3
Other orthogonally connected circuits
. 29
1.4.4
Rows
. 30
1.4.5
Columns
. 31
1.4.6
Homer's rule
. 32
1.5
Transposition and zips
. 34
1.5.1
Zipping rows together
. 35
1.6
Sequential circuits
. 36
1.6.1
Time sequences
. 37
1.6.2
Composition, parallel composition and so on
. 38
1.6.3
Delay and state
. 38
1.6.4
Timelessness
. 40
1.6.5
Slowing
. 40
Contents
1.6.6
Retiming
. 41
1.7
A systolic correlator
. 42
1.7.1
Specifying the correlator
. 42
1.7.2
Implementing the shift register
. 43
1.7.3
Eliminating the zip
. 44
1.7.4
Implementing the accumulator
. 45
1.7.5
Making the circuit systolic
. 46
1.7.6
Refining to a bit level implementation
. 49
1.7.7
Making the implementation systolic at the bit level
. 54
1.8
Butterfly networks
. 55
1.8.1
The perfect shuffle
. 55
1.8.2
Two and interleave
. 56
1.8.3
Fat composition
. 57
1.8.4
Describing the butterfly network
. 57
1.9
The Fourier transform
. 60
1.9.1
The discrete Fourier transform
. 60
1.9.2
Casting the algorithm in the notation
. 61
1.9.3
Dividing large problems into smaller ones
. 63
1.9.4
Dividing the discrete Fourier transform
. 64
1.9.5
Outline of an implementation
. 68
1.10
References
. 69
Synchronized Transitions
71
2.1
Introduction
. 71
2.2
Notation
. 72
2.2.1
Instantiation and
combinatore
. 73
2.2.2
Transition declarations
. 76
2.2.3
Cells
. 76
2.2.4
Static parameters
. 77
2.2.5
Conditional instantiation and recursion
. 77
2.2.6
Quantified instantiation
. 78
2.2.7
Restricting the use of state variables
. 79
2.3
Invariants
. 79
2.4
Examples
. 80
2.5
Tools
. 84
2.6
Synchronous realizations
. 84
2.6.1
Two-phase realizations
. 84
2.6.2
Implementation condition CREW
. 86
2.7
Mechanical verification
. 89
2.7.1
Invariants
. 89
2.7.2
LP: the Larch
Prover
. 93
2.8
Abstraction functions
. 100
2.8.1
Conditions on the abstraction function
. 102
Contents
2.8.2
Cells
.103
2.8.3
Utilizing
LP.104
2.8.4
Inheriting invariants
.105
2.8.5
The abstraction condition
.106
2.9
Delay insensitive realizations
.110
2.9.1
Implementation conditions
.112
2.9.2
Soundness of implementation conditions
.116
2.9.3
A delay insensitive FIFO
.118
2.9.4
Consequences of the implementation conditions
.122
2.9.5
Related work
.125
2.10
Conclusion
.·.126
2.11
References
.126
Verifying SECD in
HOL 129
3.1
Introduction
.129
3.2
Introducing
HOL.131
3.2.1
Conducting proofs in
HOL .132
3.2.2
Prove h(3
χ
.
(x
=
t)
Λ
A x)
=
A t
.133
3.2.3
Specifying hardware in
HOL .135
3.3
The abstract SECD machine
.138
3.4
Designing the SECD
.139
3.4.1
The chip interface
.139
3.4.2
The SECD interpreter
.141
3.4.3
The register level view
.142
3.4.4
SECD layout
.146
3.5
SECD Formal Specification
.148
3.5.1
The Low Level Definition
.148
3.5.2
Register Transfer Level
.149
3.5.3
The Top Level Specification
.153
3.6
Verification of the SECD Design
.158
3.6.1
Constraints
.158
3.6.2
Structure of the proof
.161
3.7
What Has Been Proved
.174
3.8
References
.175
Formal Ruby
179
4.1
Introduction
.179
4.1.1
Notation
.179
4.2
Signals and strong typing
.180
4.3
Puie
Ruby
.181
4.3.1
Pure Ruby type
.182
4.3.2
Ruby-extension
.183
4.4
Implementation
.187
10 Contents
4.5
Example
.188
4.6
Summary
.189
4.7
References
.190
5
Formal System Design
191
5.1
Introduction
.191
5.1.1
Modelling
.191
5.1.2
Specification
.192
5.1.3
Abstraction
.193
5.1.4
Validation
.194
5.2
Modelling Digital Behaviour
.195
5.2.1
Functional Models
.197
5.2.2
The Relational Model
.198
5.2.3
A Calculus of Behaviours
.200
5.2.4
Verification Requirements
.205
5.2.5
Abstractions
.206
5.2.6
Rules of Logic
.207
5.2.7
Summary
.209
5.3
Goal-Directed Design
.210
5.3.1
Goal-Directed Problem Solving
.211
5.3.2
Proof-Search as Problem Solving
.212
5.3.3
Modelling the Design State
.:.213
5.3.4
Formalising Design Refinement
.215
5.3.5
Example
.218
5.4
Abstraction
.222
5.4.1
Data Abstraction
.222
5.4.2
Temporal Abstraction
.225
5.4.3
Eliminating Abstractions
.228
5.5
Top-Down Design
.229
5.5.1
Example
—-
an IIR Filter
.229
5.5.2
The Real World
.232
5.6
Acknowledgements
.233
5.7
References
.233
β
Synthesis of Asynchronous VLSI Circuits
237
6.1
Introduction
.237
6.2
Communicating Hardware Processes
.238
6.2.1
Data Types and Assignment
. . 238
6.2.2
Arrays
.239
6.2.3
Composition Operators
.239
6.2.4
Control Structures
.240
6.2.5
The Replication Construct
.241
6.2.6
Procedures and Functions
.243
Contents 11
6.2.7
Concurrent Processes
.244
6.2.8
Examples
.247
6.3
The Object Code, Production Rules
.251
6.3.1
Definitions
.251
6.3.2
Switching circuits
.252
6.3.3
Operators
.253
6.3.4
The Standard Operators
.255
6.3.5
Multi-Input Operators
.257
6.3.6
Arbiter and Synchronizer
.258
6.4
The Compilation Method
. . 258
6.4.1
Process Decomposition
.258
6.4.2
Handshaking Expansion
.259
6.4.3
Lazy-active protocol
.263
6.4.4
Production-rule Expansion
.264
6.4.5
Sequencing and Stability
.264
6.4.6
Example
1:
The (L/R) process
.267
6.4.7
Operator Reduction
.269
6.4.8
Symmetrization
.270
6.4.9
Isochronic Porks
.270
6.4.10
Example
2:
A one-place buffer
.272
6.4.11
Example
3:
Single-Variable Register
.273
6.5
Case Study: Distributed Mutual Exclusion
.276
6.5.1
First Solution
.277
6.5.2
Exercise: Implementation without reshuffling
.280
6.6
References
.281
7
A Formal Introduction to a Simple HDL
285
7.1
Introduction
.285
7.2
Hardware Verification
.286
7.3
The Boyer-Moore Logic
.288
7.3.1
Bit-Vectors
.288
7.3.2
Boyer-Moore List Constants and Basic Definitions
. . . 289
7.4
Introduction to Circuit Generators
.294
7.5
Boxlist Syntax
.298
7.6
Hardware Interpreters
.301
7.6.1
The Logical Value Interpreter
.302
7.6.2
Other Interpreters
.306
7.7
A Simple Circuit Generator
.309
7.8
A Heuristically Guided Adder Generator
.314
7.9
An
ALÜ
Generator
.317
7.10
Translating our HDL into a Commercial CAD Language
. 324
7.11
Conclusions
.325
7.12
References
.327 |
| any_adam_object | 1 |
| building | Verbundindex |
| bvnumber | BV004460909 |
| classification_rvk | ST 195 |
| classification_tum | ELT 272f |
| ctrlnum | (OCoLC)24740739 (DE-599)BVBBV004460909 |
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| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift gnd-content |
| genre_facet | Konferenzschrift |
| id | DE-604.BV004460909 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T13:19:33Z |
| institution | BVB |
| institution_GND | (DE-588)16121943-3 |
| isbn | 0444888586 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-002765276 |
| oclc_num | 24740739 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-384 DE-739 DE-29T |
| owner_facet | DE-91 DE-BY-TUM DE-384 DE-739 DE-29T |
| physical | 329 S. graph. Darst. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
| publishDateSort | 1990 |
| publisher | North-Holland |
| record_format | marc |
| series2 | IFIP WG 10 5 lecture notes |
| spelling | Formal methods for VLSI design ed. by Jørgen Staunstrup Amsterdam u.a. North-Holland 1990 329 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier IFIP WG 10 5 lecture notes Literaturangaben Integrated circuits Very large scale integration Computer-aided design Integrated circuits Very large scale integration Testing Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Algorithmus (DE-588)4001183-5 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift gnd-content VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s DE-604 Schaltungsentwurf (DE-588)4179389-4 s Algorithmus (DE-588)4001183-5 s 1\p DE-604 Staunstrup, Jørgen Sonstige oth International Summer School on Formal Methods for VLSI Design 1990 Kopenhagen Sonstige (DE-588)16121943-3 oth Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002765276&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Formal methods for VLSI design Integrated circuits Very large scale integration Computer-aided design Integrated circuits Very large scale integration Testing Schaltungsentwurf (DE-588)4179389-4 gnd Entwurf (DE-588)4121208-3 gnd Algorithmus (DE-588)4001183-5 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4121208-3 (DE-588)4001183-5 (DE-588)4117388-0 (DE-588)1071861417 |
| title | Formal methods for VLSI design |
| title_auth | Formal methods for VLSI design |
| title_exact_search | Formal methods for VLSI design |
| title_full | Formal methods for VLSI design ed. by Jørgen Staunstrup |
| title_fullStr | Formal methods for VLSI design ed. by Jørgen Staunstrup |
| title_full_unstemmed | Formal methods for VLSI design ed. by Jørgen Staunstrup |
| title_short | Formal methods for VLSI design |
| title_sort | formal methods for vlsi design |
| topic | Integrated circuits Very large scale integration Computer-aided design Integrated circuits Very large scale integration Testing Schaltungsentwurf (DE-588)4179389-4 gnd Entwurf (DE-588)4121208-3 gnd Algorithmus (DE-588)4001183-5 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Integrated circuits Very large scale integration Computer-aided design Integrated circuits Very large scale integration Testing Schaltungsentwurf Entwurf Algorithmus VLSI Konferenzschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002765276&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT staunstrupjørgen formalmethodsforvlsidesign AT internationalsummerschoolonformalmethodsforvlsidesignkopenhagen formalmethodsforvlsidesign |