Proceedings:
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Berlin [u.a.]
vde-Verl.
1991
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | 532 S. Ill., graph. Darst. |
| ISBN: | 3800717786 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV004329511 | ||
| 003 | DE-604 | ||
| 005 | 20190430 | ||
| 007 | t | ||
| 008 | 910304s1991 gw ad|| |||| 10||| eng d | ||
| 020 | |a 3800717786 |9 3-8007-1778-6 | ||
| 035 | |a (OCoLC)165595560 | ||
| 035 | |a (DE-599)BVBBV004329511 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 044 | |a gw |c DE | ||
| 049 | |a DE-12 |a DE-91 |a DE-83 |a DE-188 |a DE-29T | ||
| 082 | 0 | |a 621.3815/0287 | |
| 084 | |a ZN 4940 |0 (DE-625)157423: |2 rvk | ||
| 084 | |a ELT 359f |2 stub | ||
| 111 | 2 | |a ETC |n 2 |d 1991 |c München |j Verfasser |0 (DE-588)2116251-7 |4 aut | |
| 245 | 1 | 0 | |a Proceedings |c ETC 91 ; 2. European Test Conference, Munich, April 10 - 12, 1991 |
| 264 | 1 | |a Berlin [u.a.] |b vde-Verl. |c 1991 | |
| 300 | |a 532 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Datenverarbeitung |0 (DE-588)4011152-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Prüftechnik |0 (DE-588)4047610-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Diagnosesystem |0 (DE-588)4149458-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Mikroelektronik |0 (DE-588)4039207-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Test |0 (DE-588)4059549-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 1991 |z München |2 gnd-content | |
| 689 | 0 | 0 | |a Datenverarbeitung |0 (DE-588)4011152-0 |D s |
| 689 | 0 | 1 | |a Test |0 (DE-588)4059549-3 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Mikroelektronik |0 (DE-588)4039207-7 |D s |
| 689 | 1 | 1 | |a Prüftechnik |0 (DE-588)4047610-8 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
| 689 | 2 | 1 | |a Diagnosesystem |0 (DE-588)4149458-1 |D s |
| 689 | 2 | |5 DE-188 | |
| 856 | 4 | 2 | |m Digitalisierung TU Muenchen |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002691961&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-002691961 | ||
Datensatz im Suchindex
| _version_ | 1804118517134393344 |
|---|---|
| adam_text | Table
of contents
Session
1: 1149.1
Compatible Test Chips
Chair: K. Parker, Hewlett-Packard, USA
Coordinator: C. Maunder, BTRL, UK
Paper
1.1:
The Boundary-Scan Master: Architecture and Implementation
.......... 1
N.
Jarwala,
С
W.
Yau
AT
&
Τ
Bell Labs. USA
Paper
1.2:
Self-Test of a
256
к
χ
4
bit Stand-Alone Static RAM
................... 11
R. H. A.
Rijk,
R.
W.
С.
Dekker,
H. G.
Kerkhoff
University of Twente, The Netherlands
Paper
1.3:
Boundary Scan and BIST Compatible IEEE
1149.1 :
VHDL
&
Autosynthesis
Design of a SRAM Tester Macrocell and Chip
.................................. 17
S.
Kritter,
E. Mackowiak
SGS-Thomson Microelectronics, France
Session
2:
Stimuli Generation and Signature Analysis in BIST Structures
Chair: T. W. Williams, IBM, USA
Co-ordinator:
E. Aas,
Trondheim
University, Norway
Paper
2.1 :
LFSR based Deterministic and
Pseudo-
Random Test Pattern Generator
Structures
............................................................ 27
С
Dufaza, G. Cambon
LAMM, France
Paper
2.2: 1С
Realization of a Cellular Automata Based Self-Test Strategy for
Programmable Data Paths
................................................ 35
J. van
Sas, F.
Catthoor,
S. Vernalde
IMEC Laboratory, Belgium
Paper
2.3:
Experimental Analysis of Fault Coverage in Systems with Signature
Registers
............................................................. 45
J.
Rajski,
J. Tyszer
McGill University, Canada
Session
3:
BIST of Regular Structures
Chair: V. Yarmolik, Minsk Radio
Eng.
Institute, USSR
Co-ordinator: J.-L Becu, SGS-Thomson Microelectronics,
France
Paper
3.1 :
A Universal Test Algorithm for the Self-Test of Parametrizable Random
Access Memories
...................................................... 53
H. C
Ritter,
Th. M. Schwair
Siemens,
Germany
Paper
3.2:
Test Pattern Generators for Arithmetic and Logic Units
................ 61
M. Nicolaidis
IMAG/TIM3,
France
Paper
3.3:
Parallel Self-Test and the Synthesis of Control Units
.................. 73
B. Eschermann,
H. -J.
Wunderlich
Karlsruhe University, Germany
Session
4:
Advances in
1С
Defects-Based Testability
Chair: C. Hawkins, University of New Mexico, USA
Co-ordinator:
C. Landrault
LAMM, France
Paper
4.1 :
Defect and Design Error Diagnosability Measure
W. Maly, S. Naik
Carnegie Mellon University, USA
83
Paper 4.2:
Quantifying Non-Target Defect Detection by Target Fault Test Sets
K. M. Butler, M. R. Mercer
Texas University, USA
Paper
4.3:
Layout-Driven Testability Enhancement
J. P.
Teixeira,
F. M.
Concalves,
J. J. T.
Sousa
INESC, Portugal
91
101
Session
5:
Board and
System
Fault
Location
Chair:
M.
Mezzalama,
Politecnico di
Torino, Italy
Co-ordinator: D. Laurent Bull Systems, France
Paper
5.1 :
Test Data Collecting System: A Paperless Test, Troubleshoot and Repair
.. 111
L. Daemen
Alcatel Bell, Belgium
Paper
5.2:
Troubleshooting Digital Circuit Boards by Means of an Expert System:
An Approach at Alcatel Bell
................................................123
J. Vanwelkenhuysen
Vrije
University, Belgium
Paper
5.3:
Distributed Diagnosis of Faults in a Multiple-Path
Multi-Stage Interconnection Network
........................................133
S-J. Wang
Princeton University, USA
Session
6:
Advances in CMOS/BICMOS Testing
Chair: W. Maly, Carnegie-Mellon University, USA
Co-ordinator: C. Lopez-Barrio, Telefonica I
+
D, Spain
Paper
6.1 :
Fault Modelling of Gate Oxide Shorts Gloating Gate and
Bridging Failures in CMOS Circuits
..........................................143
V. H. Champac, R. Rodriguez-
Montanes,
J.
A. Segura,
J. Figueras, J.
A. Rubio
UPC, Spain
Paper
6.2:
Comparing Stuck Fault and Current Testing via CMOS Chip Test
..........149
T. Storey, W. Maly, J. Andrews,
M. Miske
Carnegie Mellon University, National Semiconductor, USA
Paper
6.3:
Failure Mechanisms in BiCMOS Sea-of-Gate Arrays
...................157
W. Denner, G.
Tröster,
Α.
Wedel,
E. Zocher
Telefunken, Germany
Session
7:
High-Performance Fault Simulation
Chair: M.
Kessler, IBM Deutschland,
Germany
Co-ordinator: M.
Melgara,
CSELT,
Italy
Paper
7.1 :
Vector Length Control for Compiled Code Event Driven Pattern Parallel
Fault Simulation
.........................................................165
W. Daehn, D.
Kannemacher,
J.
Castagne
Hannover University, Germany
Paper
7.2:
An Efficient Parallel Pattern Gate Delay Fault Simulator with
Accelerated Detected Fault Size Determination Capabilities
...... ... 171
F. Fink, K.
Fuchs,
M. H.
Schulz
TU
Munich,
Siemens,
Germany
Paper
7.3: Switch-Level Fault
Simulation by Critical Path Tracing
..................181
M.
Dalpasso,
M.
Favalli, P.
Olivo,
В.
Ricco
Bologna
University, Italy
Session 8: Standards
for Test-
Information
Interchange
Chair: H.
Wojtkowiak,
University of
Siegen,
Germany
Co-ordinator:
M.
Wahl,
University
of
Siegen,
Germany
Paper 8.1 :
A User s Introduction to WAVES
................................... 191
R. Hillman, F. Koo, L. Shombert
RADC, Hughes Aircraft, Harris Corporation, USA
Paper
8.2:
EDIF as a Standard Test Specification Format
....................... 201
P. Vandeloo
IMEC, Belgium
Paper
8.3:
An Automatic Test Program Generation Strategy Using a
Tester-Independent Waveform Representation
............................... 209
Louis Testa, R. Lunde
TSSI, Beaverton, USA
Session
9:
Fault Simulation and ATPG
Chair: C. Almeida, INESC, Portugal
Co-ordinator: M.
Schulz,
Siemens-
Nixdorf,
Germany
Paper
9.1 :
Testing Finite State Machines Implemented by Programmable Logic
Devices
.............................................................. 217
F.
Corsi,
S.
Martino,
A. L. Sangiovanni-VincentelH
Bari
University, Italy; Berkeley University, USA
Paper
9.2:
Distributed Fault Simulation with Vector Set Partitioning
............... 227
A. Warshawsky, J.
Rajski
McGill University, Canada
Paper
9.3:
LFSR-Coded Test Patterns for Scan Designs
........................ 237
B. Koenemann
IBM, USA
Session
10:
Scan Optimisation Techniques
Chair: J. Jamieson, Alcatel, Belgium
Co-ordinator: F. Beenker, Philips Research, The Netherlands
Paper
10.1 :
A Model for Test-Time Reduction of Scan Testable Circuits
............ 243
S. Oosdikj, F. Beenker,
L
Thijssen
Philips Research Labs, Delft University, The Netherlands
Paper
10.2:
Test Point Insertion for Scan-Based BIST
.......................... 253
B. H. Seiss, P. M. Trouborst,
M. H.
Schulz
TU
Munich, Germany; Bell-Northern Research, Canada; Siemens, Germany
Paper
10.3:
A Methodology for Partial Scan Design
........................... 263
D. Pradhan, S.
Nori,
J. Swaminathan
Massachusetts University, Amdahl Corp., USA
Session
11:
Advanced ATPG
Chair: G. Saucier, INPG/CSI, France
Co-ordinator: E. Trischler, Siemens-
Nixdorf,
Germany
Paper
11.1 :
Mixed Level Automatic Test Pattern Generation for CMOS Circuits
...... 273
M. L
Flottes,
C. Landrault, S.
Paul,
S. Pravossoudovitch
LAMM, France
Paper
11.2:
MINOTAUR
-
A Mixed Level Test Pattern Generator for VLSI Circuits
___ 283
J. M.
С
Geada,
G.
Russell
Newcastle upon Tyne University, UK
Paper
11.3:
Advanced Techniques for Sequential Test Generation
................ 293
N.
Gouders, R. Kaibel
Duisburg
University, Germany
Session
12:
Analogue and Mixed-Signal Testing
Chair: K. Baker, Philips Research Labs., The Netherlands
Co-ordinator: J.-P.
Teixeira, INESC,
Portugal
Paper
12.1:
A Novel Technique for Testing Mixed-Signal I. C. s
.................. 301
P. S. Evans, M. A. Al-Qutayri, P. R. Shepherd
Bath University, UK
Paper
12.2:
Hybrid Built-in Self-Test (HBIST) for Mixed Analogue/Digital
Integrated Circuits
..................................................... 307
M. J. Ohletz
Hannover University, Germany
Paper
12.3:
Automatic Test of T1 and CEPT Line Interface Units
................. 317
D.
J. Derian
LXX,
USA
Session
13:
Testable Design through Testability Analysis
Chair: J. Soden,
Sandia
Labs., USA
Co-ordinator: P. Prinetto,
Politecnico di
Torino, Italy
Paper
13.1:
Hierarchical Functional Level Testability Analysis
................... 327
B. H. Nairn,
B. Kaminska
Montreal Polytechnic, Canada
Paper
13.2:
On Bridging Fault Controllability and Observability and Their
Correlations to Detectability
.............................................. 333
R. Kapur, K. M. Butler, M. R. Mercer
Texas University, USA
Paper
13.3:
Trade-off Analysis of the Effectiveness of Testability Estimators
....... 341
R. Kapur, J. Ferguson, M. Abadir
Texas University, USA
Session
14:
High-Performance Fixturing in
1С
Testing
Chair: A. Wakeling, Schlumberger, UK
Co-ordinator: F. Pool, Philips Components, The Netherlands
Paper
14.1 :
Impedance Matching Circuit for Dynamic Correction of Device/ATE
Impedance Mismatch
................................................... 351
M. C. Kohalmy
Teradyne, USA
Paper
14.2:
High Speed Fixturing of Chips and Wafers for Electron Beam Probing
.. 361
K.
Helmreich,
M. Chowanetz
Erlangen-Nürnberg
University, Germany
Paper 14.3: Groundbounce in
ASIC s: Modelling and Test Results
................ 367
L.
Diaz-Olavarrieta
Bell, Canada
Session 15:
Boundary Scan in Practice
Chair:
R.
Tulloss,
AT
&
T
Bell Labs., USA
Co-ordinator: C.
Maunder,
BTRL, UK
Paper 15.1 :
A Test Economics
Model &
Cost-Benefit Analysis of Boundary Scan
. .. 375
J. Miles,
R. De
Bondt, L. Daemen
Alcatel Bell, Belgium
Paper
15.2:
Built-in Pad Test with Boundary Scan
............................ 385
T. Schwederski, T.
Büchner,
J. Leenstra, G.
Roos,
L
Spaanenburg
Institute for Microelectronics Stuttgart, Germany
Paper
15.3:
Assessing Fault Coverage in Virtual
Incircuit
Testing of Partial
Boundary-Scan
....................................................... 393
P.
Hansen
Teradyne USA
Session
16:
Test Pattern Preparation
Chair: M.
Gemer,
Siemens, Germany
Co-ordinator: W. Daehn, Sican, Germany
Paper
16.1 :
Intent Documentation in a Graphical Test Programme Editor Simplifies
the Logic Simulator
—
Tester Link
.......................................... 397
ft W. Werthebach
Braunschweig University, Germany
Paper
16.2:
Device-Oriented Test Program Generation using the Sequencer-Per-Pin
Test System Architecture
................................................. 405
C. Tinaztepe, P. David
Schlumberger USA; Schlumberger France
Paper
16.3:
High Level Representation of ATE Patterns
......................... 413
A. ft Taylor
LTX/Trillium, USA
Session
17:
Macrotest
Tools and Techniques
Chair: G. Robinson, GenRad, USA
Co-ordinator: B.
Courtois,
IMAG/TIM3,
France
Paper
17.1 :
Interactive Test Strategy planning: Model and a Prototype
............ 417
M. Laffitte
Siemens, Germany
Paper
17.2:
Minimization of Test Control Blocks
.............................. 427
E. J.
Marinissen,
R.
Dekker
Philips Research
Labs, The Netherlands
Paper
17.3:
An Economics Based Test Strategy Planner for VLSI Design
........... 437
C. Dislis, J. Dick, A. P. Ambler
Brunei University, UK
Paper
17.4:
Automatic Test-Specification Generation for Macro-Level BIST Based
on the Boundary-Scan Standard
.......................................... 447
R. P. van Riessen, H. G. Kerkhoff
University of Twente, The Netherlands
Session
18:
Test System Architectures and Performance
Chair: C. da Costa, Teradyne, Germany
Co-ordinator: F. Pool, Philips Components, The Netherlands
Paper
18.1 :
Performance Characteristics of a IGbps Digital Test System
........... 455
D. C. Keezer
South Florida University, USA
Paper
18.2:
Implementing Per-Pin Architecture VLSI for WLR EM parametric testing
. 463
E.
Weis,
E. Kinsbron,
A. Cohen,
G. Chánoch,
В.
Vogel,
N.
Croitoru
Tel
Aviv University, Israel
Paper
18.3:
Remote Communications on the Tester Workstation
................. 467
D. Dowding
LTX/Trillium, USA
Paper
18.4:
Graphic Displays for
Non
-Graphic Test Data
....................... 473
A. E. Downey
Ando
Corporation, USA
Posters
Poster:
Production
Method Using IEEE
1149.1
Today
479
Jan
-
Erik Rickegard, Schlumberger ATE, Sweden
Poster: Intelligent Probe Sample Placement
........................................... 480
C. G.
McKay, Schlumberger Technologies, UK
Poster: Integrating Design for Test Through Concurrent Engineering
—
Practical
Implementations
........................................................... 481
Jon
Turino,
Logical Solutions Technology, Inc., USA
Poster: On the Selection of a Partial Scan Path with Respect to Target Faults
................. 482
Harald
Gundlach, University
Erlangen-Nürnberg,
Germany
Poster: The Design and Implementation of an Efficient Method to Generate Protocol
Conf ormance Test Sequence
................................................. 483
Johnny S. K. Wong, Iowa State University, USA
Poster: CMOS Test Generation for High Fault Coverage by Switch Levelto Gate Level Coupling
. .. 484
H. T,
Vierhaus, GMD,
Germany
Poster:
Pseudoexhaustive
Test Sets Generated in LFSRs
................................. 485
Ondřej Novák,
Technical Univ. of
Liberec,
Czechoslovakia
Poster: A Fast Parallel Pattern Fault Simulator for Combinational Circuits
.................... 486
Dong S. Ha, Virginia Polytechnic Institute and State University, USA
Poster: Test Generation for Digital Systems at Functional Level
............................ 487
Krzysztof Kuchcinski,
Linköping
University, Sweden
Poster: On Parallel Test Pattern Generation Algorithms
................................... 488
Tapan
J.
Chakraborty, AT
&
T
Bell Laboratories, USA
Poster: Logical Layer Conformance Testing of Parallel Bus Interfaces
....................... 489
Bernhard
Müller, Forschungszentrum Informatik,
Germany
Poster:
Modular Testing of a VLSI Processor Chip Using the BED System
.................... 490
Bernd Hanstein,
Siemens, Germany
Poster: An
Е
-Beam
Prober
Based VLSI Device Characterization System
..................... 491
Peter Cundall, Schlumberger Technologies, USA
Poster: An
E
-Beam
Prober
Based VLSI Device Characterization System
..................... 491
Peter Cundall, Schlumberger Technologies, USA
Poster: VLSI Logic Verification Program Generator
...................................... 492
Ajit Dingankar, Tien
N.
Le,
IBM Corporation, USA
Poster: Towards Functional Testing From a VHDL Data Flow Description
..................... 493
P. Wodey,
Lab. de
Genie
Informatique,
France
Poster: Simplified Test Strategies for Analogue Integrated Circuits
......................... 494
A. P. Dorey University of Lancaster, UK
Poster:
Е
-Beam Testing For Microprocessor Failure Location
............................. 495
J. Cabestany, UPC, Spain
Poster: improved Probing in Analogue Diagnosis
....................................... 496
Antony Wakeling, Schlumberger Technologies, UK
Poster: Design
&
Test Integration
.................................................... 497
Ruedi H. Egger, GenRad, Switzerland
Poster: Integral Test
Strategy for Telecommunications Line-
Cards ..........................498
Dirk van de Lagemaat, Philips
Communication
Systems, The Netherlands
Poster:
A Hierarchical
Test Generator
for CMOS Bridging Faults ...........................
499
Will
R.
Moore,
University of
Oxford,
UK
Poster:
Functional
Model
and Self-Testing in VHDLfor Functional Test Generation
............. 500
Heinz-Dieter Hummer,
University of
Duisburg,
Germany
Poster: PATSIM: An Automatic Test Pattern Generator in DISIM
............................ 501
Harbhajan Singh, Daimler-Benz, Germany
Poster: A New Algorithm for Diagnosing Interconnect Faults on Boundary Scan Boards
........ 502
José
Manuel M.
Ferreira, INESC,
Portugal
Poster: A New Prototype for ASIC Functional Testing
.................................... 503
Carlos
Beltán,
INESC, Portugal
Poster: A New Path Delay Fault Simulation Algorithm
.................................... 504
Yuejian Wu, University of British Columbia, Canada
Poster: Algorithms for VLSI Error Location Applied to an
E
-Beam Validation System
........... 505
P. Garino,
CSELT,
Italy
Poster: Timing Oriented Testing for VLSIs
............................................. 506
Frank Dymann, Siemens, Germany
Poster: Probability Driven Partial Scan Design
.......................................... 507
Chung
Len
Lee, National Chiao Tung University, Taiwan,
R.O.C.
Poster: Digital Simulators in Test; Conversion of Waveforms to Test Language
................ 508
Gordon F. Taylor, GenRad, USA
Poster: Using Emulation Techniques In General Purpose ATE
..............................509
R. Wade Williams, GenRad, USA
Poster: Phoebus: A Tool for Hierarchical Testability and Redundancy Analysis
................ 510
Jean-Claude Geffroy INSAT/DGE/GERII, France
Poster: Boundary Scan Design for a Memory Controller
.................................. 511
Реѓел
L
Harrod, Advanced RISC Machines Ltd., UK
Poster: Developments for Built-in-Self-Test of Mixed ASICs
.............................. 512
Rosemary A. Cobley, Exeter University, UK
Poster: Implementing Boundary-Scan and Pseudo-Random Built-in Self Test in a
0.7
Micron
CMOS Asynchronous Transfer Mode Switch
..................................... 513
P. Thorel,
C.N.E.T.,
France
Poster: Parsimonious Test Concept for Embedded PLAs in Boundary Scan Environment
....... 514
Einar
J.
Aas,
Norwegian Inst. of Technology, Norway
Poster: Towards Automated Diagnostic:
E
-Beam Tester Data Base Environment
.............. 515
Laurence Primot, IBM, France
Poster: Tradeoffs in Self-Test and External Test of PLAs
.................................. 516
Einar
J.
Aas,
Norwegian Inst. of Technology, Norway
Poster: Simulation for Delay Faults
................................................... 517
Y. Xing, University of Twente, The Netherlands
Poster: Hierarchical Approach to Test Pattern Generation
................................. 518
E C.
Weening, University of Twente, The Netherlands
Poster: Autonomously Testable Dynamic CMOS PLAs
................................... 519
M. Renovell, LAMM, France
Poster: A High-Level Pattern Development System Promoting Industrial Concurrent
Engineering
............................................................... 520
Gunter T.
Kramp!,
Siemens, Austria
Poster: Automatic Test Pattern and Test Program Generation
for VLSI
Scan Designs ........... 521
Friedrich Hapke, Philips
Components, Germany
Poster: Test
of
Analog
Components
in
a
Digital Environment.............................. 522
Martin Viktil, EB Technology,
Norway
Poster:
Self-Checking Circuits in Presence of Bridging Faults. Possibilities of Current
Sensing in XOR Parity Trees
.................................................. 523
Luz Balado,
UPC, Spain
Poster: Design for Contactless Testability in a Scan-Path Environment
...................... 524
Josef Gross,
Universität
Hannover, Germany
Poster: Spectrum Analysis of Small-Bandwidth Signals
Using
a Modulatet
Electron Beam
............................................. 525
W. Kern,
SEL
Alcatel, Germany
Poster: Looking for Functional Fault Equivalence
....................................... 526
Antonio Lioy,
Politecnico di
Torino, Italy
Poster: An Application of Automata Theory to sequential ATPG
............................ 527
Paolo Prinetto,
Politecnico di
Torino, Italy
Poster: Test Generation by Fault Sampling: Estimates of Population Coverage
................ 528
Hassan Farhat, University of Nebraska, USA
Poster: The Challenge of Designing a Tester that is Compatible and Different
at the Same Time
.......................................................... 529
John Doyle, GenRad, UK
Poster: Implementing a Parallel/Serial Converter for Board Scan Test
....................... 530
Jay Brown, National Semiconductor, USA
Poster: A Proposal for Extending the IEEE Standard
1149.1
Test Access Port to
System Backplanes
........................................................ 531
Dilip Bhavasar, Digital Equipment, USA
Poster: A Reduced Lost Fault Simulation Strategy for the AM29050 TM Microprocessor
......... 532
Gopi Ganapathy, Advanced Micro Devices, USA
|
| any_adam_object | 1 |
| author_corporate | ETC München |
| author_corporate_role | aut |
| author_facet | ETC München |
| author_sort | ETC München |
| building | Verbundindex |
| bvnumber | BV004329511 |
| classification_rvk | ZN 4940 |
| classification_tum | ELT 359f |
| ctrlnum | (OCoLC)165595560 (DE-599)BVBBV004329511 |
| dewey-full | 621.3815/0287 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815/0287 |
| dewey-search | 621.3815/0287 |
| dewey-sort | 3621.3815 3287 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02032nam a2200505 c 4500</leader><controlfield tag="001">BV004329511</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20190430 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">910304s1991 gw ad|| |||| 10||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">3800717786</subfield><subfield code="9">3-8007-1778-6</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)165595560</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV004329511</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">gw</subfield><subfield code="c">DE</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-12</subfield><subfield code="a">DE-91</subfield><subfield code="a">DE-83</subfield><subfield code="a">DE-188</subfield><subfield code="a">DE-29T</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815/0287</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4940</subfield><subfield code="0">(DE-625)157423:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 359f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="111" ind1="2" ind2=" "><subfield code="a">ETC</subfield><subfield code="n">2</subfield><subfield code="d">1991</subfield><subfield code="c">München</subfield><subfield code="j">Verfasser</subfield><subfield code="0">(DE-588)2116251-7</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Proceedings</subfield><subfield code="c">ETC 91 ; 2. European Test Conference, Munich, April 10 - 12, 1991</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Berlin [u.a.]</subfield><subfield code="b">vde-Verl.</subfield><subfield code="c">1991</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">532 S.</subfield><subfield code="b">Ill., graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Datenverarbeitung</subfield><subfield code="0">(DE-588)4011152-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Prüftechnik</subfield><subfield code="0">(DE-588)4047610-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Diagnosesystem</subfield><subfield code="0">(DE-588)4149458-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Mikroelektronik</subfield><subfield code="0">(DE-588)4039207-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Test</subfield><subfield code="0">(DE-588)4059549-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)1071861417</subfield><subfield code="a">Konferenzschrift</subfield><subfield code="y">1991</subfield><subfield code="z">München</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Datenverarbeitung</subfield><subfield code="0">(DE-588)4011152-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Test</subfield><subfield code="0">(DE-588)4059549-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Mikroelektronik</subfield><subfield code="0">(DE-588)4039207-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Prüftechnik</subfield><subfield code="0">(DE-588)4047610-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2="1"><subfield code="a">Diagnosesystem</subfield><subfield code="0">(DE-588)4149458-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="5">DE-188</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Digitalisierung TU Muenchen</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002691961&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-002691961</subfield></datafield></record></collection> |
| genre | (DE-588)1071861417 Konferenzschrift 1991 München gnd-content |
| genre_facet | Konferenzschrift 1991 München |
| id | DE-604.BV004329511 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T16:11:33Z |
| institution | BVB |
| institution_GND | (DE-588)2116251-7 |
| isbn | 3800717786 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-002691961 |
| oclc_num | 165595560 |
| open_access_boolean | |
| owner | DE-12 DE-91 DE-BY-TUM DE-83 DE-188 DE-29T |
| owner_facet | DE-12 DE-91 DE-BY-TUM DE-83 DE-188 DE-29T |
| physical | 532 S. Ill., graph. Darst. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| publisher | vde-Verl. |
| record_format | marc |
| spelling | ETC 2 1991 München Verfasser (DE-588)2116251-7 aut Proceedings ETC 91 ; 2. European Test Conference, Munich, April 10 - 12, 1991 Berlin [u.a.] vde-Verl. 1991 532 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Datenverarbeitung (DE-588)4011152-0 gnd rswk-swf Prüftechnik (DE-588)4047610-8 gnd rswk-swf Diagnosesystem (DE-588)4149458-1 gnd rswk-swf Mikroelektronik (DE-588)4039207-7 gnd rswk-swf Test (DE-588)4059549-3 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1991 München gnd-content Datenverarbeitung (DE-588)4011152-0 s Test (DE-588)4059549-3 s DE-604 Mikroelektronik (DE-588)4039207-7 s Prüftechnik (DE-588)4047610-8 s Integrierte Schaltung (DE-588)4027242-4 s Diagnosesystem (DE-588)4149458-1 s DE-188 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002691961&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings Datenverarbeitung (DE-588)4011152-0 gnd Prüftechnik (DE-588)4047610-8 gnd Diagnosesystem (DE-588)4149458-1 gnd Mikroelektronik (DE-588)4039207-7 gnd Test (DE-588)4059549-3 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| subject_GND | (DE-588)4011152-0 (DE-588)4047610-8 (DE-588)4149458-1 (DE-588)4039207-7 (DE-588)4059549-3 (DE-588)4027242-4 (DE-588)1071861417 |
| title | Proceedings |
| title_auth | Proceedings |
| title_exact_search | Proceedings |
| title_full | Proceedings ETC 91 ; 2. European Test Conference, Munich, April 10 - 12, 1991 |
| title_fullStr | Proceedings ETC 91 ; 2. European Test Conference, Munich, April 10 - 12, 1991 |
| title_full_unstemmed | Proceedings ETC 91 ; 2. European Test Conference, Munich, April 10 - 12, 1991 |
| title_short | Proceedings |
| title_sort | proceedings |
| topic | Datenverarbeitung (DE-588)4011152-0 gnd Prüftechnik (DE-588)4047610-8 gnd Diagnosesystem (DE-588)4149458-1 gnd Mikroelektronik (DE-588)4039207-7 gnd Test (DE-588)4059549-3 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| topic_facet | Datenverarbeitung Prüftechnik Diagnosesystem Mikroelektronik Test Integrierte Schaltung Konferenzschrift 1991 München |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002691961&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT etcmunchen proceedings |