Hierarchical modeling for VLSI circuit testing:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston [u.a.]
Kluwer Acad. Press
1990
|
| Schriftenreihe: | The Kluwer international series in engineering and computer science
89 |
| Schlagworte: | |
| Beschreibung: | X, 159 S. graph. Darst. |
| ISBN: | 079239058X |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV004135952 | ||
| 003 | DE-604 | ||
| 005 | 20140613 | ||
| 007 | t | ||
| 008 | 901105s1990 d||| |||| 00||| engod | ||
| 020 | |a 079239058X |9 0-7923-9058-X | ||
| 035 | |a (OCoLC)20629415 | ||
| 035 | |a (DE-599)BVBBV004135952 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91 |a DE-739 |a DE-29T |a DE-898 |a DE-11 | ||
| 050 | 0 | |a TK7874 | |
| 082 | 0 | |a 621.39/5/0287 |2 20 | |
| 084 | |a ST 190 |0 (DE-625)143607: |2 rvk | ||
| 084 | |a ELT 272f |2 stub | ||
| 084 | |a ELT 238f |2 stub | ||
| 100 | 1 | |a Bhattacharya, Debashis |d 1961- |e Verfasser |0 (DE-588)120125870 |4 aut | |
| 245 | 1 | 0 | |a Hierarchical modeling for VLSI circuit testing |c by Debashis Bhattacharya and John P. Hayes |
| 264 | 1 | |a Boston [u.a.] |b Kluwer Acad. Press |c 1990 | |
| 300 | |a X, 159 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a The Kluwer international series in engineering and computer science |v 89 | |
| 650 | 4 | |a Circuit intégré | |
| 650 | 7 | |a Circuits intégrés à très grande échelle |2 ram | |
| 650 | 4 | |a VLSI | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Computer simulation | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Testing | |
| 650 | 0 | 7 | |a Simulation |0 (DE-588)4055072-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Test |0 (DE-588)4059549-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Prüftechnik |0 (DE-588)4047610-8 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 1 | |a Prüftechnik |0 (DE-588)4047610-8 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 1 | 1 | |a Test |0 (DE-588)4059549-3 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
| 689 | 2 | |5 DE-604 | |
| 689 | 3 | 0 | |a Simulation |0 (DE-588)4055072-2 |D s |
| 689 | 3 | |5 DE-604 | |
| 700 | 1 | |a Hayes, John P. |e Verfasser |4 aut | |
| 830 | 0 | |a The Kluwer international series in engineering and computer science |v 89 |w (DE-604)BV023545171 |9 89 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-002580301 | ||
Datensatz im Suchindex
| _version_ | 1804118350493646848 |
|---|---|
| any_adam_object | |
| author | Bhattacharya, Debashis 1961- Hayes, John P. |
| author_GND | (DE-588)120125870 |
| author_facet | Bhattacharya, Debashis 1961- Hayes, John P. |
| author_role | aut aut |
| author_sort | Bhattacharya, Debashis 1961- |
| author_variant | d b db j p h jp jph |
| building | Verbundindex |
| bvnumber | BV004135952 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874 |
| callnumber-search | TK7874 |
| callnumber-sort | TK 47874 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 190 |
| classification_tum | ELT 272f ELT 238f |
| ctrlnum | (OCoLC)20629415 (DE-599)BVBBV004135952 |
| dewey-full | 621.39/5/0287 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5/0287 |
| dewey-search | 621.39/5/0287 |
| dewey-sort | 3621.39 15 3287 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02206nam a2200589 cb4500</leader><controlfield tag="001">BV004135952</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20140613 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">901105s1990 d||| |||| 00||| engod</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">079239058X</subfield><subfield code="9">0-7923-9058-X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)20629415</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV004135952</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield><subfield code="a">DE-739</subfield><subfield code="a">DE-29T</subfield><subfield code="a">DE-898</subfield><subfield code="a">DE-11</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7874</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5/0287</subfield><subfield code="2">20</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 190</subfield><subfield code="0">(DE-625)143607:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 272f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 238f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Bhattacharya, Debashis</subfield><subfield code="d">1961-</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)120125870</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Hierarchical modeling for VLSI circuit testing</subfield><subfield code="c">by Debashis Bhattacharya and John P. Hayes</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston [u.a.]</subfield><subfield code="b">Kluwer Acad. Press</subfield><subfield code="c">1990</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">X, 159 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">The Kluwer international series in engineering and computer science</subfield><subfield code="v">89</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuit intégré</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Circuits intégrés à très grande échelle</subfield><subfield code="2">ram</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">VLSI</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Computer simulation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Testing</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Simulation</subfield><subfield code="0">(DE-588)4055072-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Test</subfield><subfield code="0">(DE-588)4059549-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Prüftechnik</subfield><subfield code="0">(DE-588)4047610-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Prüftechnik</subfield><subfield code="0">(DE-588)4047610-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Test</subfield><subfield code="0">(DE-588)4059549-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="3" ind2="0"><subfield code="a">Simulation</subfield><subfield code="0">(DE-588)4055072-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Hayes, John P.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">The Kluwer international series in engineering and computer science</subfield><subfield code="v">89</subfield><subfield code="w">(DE-604)BV023545171</subfield><subfield code="9">89</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-002580301</subfield></datafield></record></collection> |
| id | DE-604.BV004135952 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T16:08:54Z |
| institution | BVB |
| isbn | 079239058X |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-002580301 |
| oclc_num | 20629415 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-739 DE-29T DE-898 DE-BY-UBR DE-11 |
| owner_facet | DE-91 DE-BY-TUM DE-739 DE-29T DE-898 DE-BY-UBR DE-11 |
| physical | X, 159 S. graph. Darst. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
| publishDateSort | 1990 |
| publisher | Kluwer Acad. Press |
| record_format | marc |
| series | The Kluwer international series in engineering and computer science |
| series2 | The Kluwer international series in engineering and computer science |
| spelling | Bhattacharya, Debashis 1961- Verfasser (DE-588)120125870 aut Hierarchical modeling for VLSI circuit testing by Debashis Bhattacharya and John P. Hayes Boston [u.a.] Kluwer Acad. Press 1990 X, 159 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier The Kluwer international series in engineering and computer science 89 Circuit intégré Circuits intégrés à très grande échelle ram VLSI Integrated circuits Very large scale integration Computer simulation Integrated circuits Very large scale integration Testing Simulation (DE-588)4055072-2 gnd rswk-swf Test (DE-588)4059549-3 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Prüftechnik (DE-588)4047610-8 gnd rswk-swf VLSI (DE-588)4117388-0 s Prüftechnik (DE-588)4047610-8 s DE-604 Test (DE-588)4059549-3 s Integrierte Schaltung (DE-588)4027242-4 s Simulation (DE-588)4055072-2 s Hayes, John P. Verfasser aut The Kluwer international series in engineering and computer science 89 (DE-604)BV023545171 89 |
| spellingShingle | Bhattacharya, Debashis 1961- Hayes, John P. Hierarchical modeling for VLSI circuit testing The Kluwer international series in engineering and computer science Circuit intégré Circuits intégrés à très grande échelle ram VLSI Integrated circuits Very large scale integration Computer simulation Integrated circuits Very large scale integration Testing Simulation (DE-588)4055072-2 gnd Test (DE-588)4059549-3 gnd VLSI (DE-588)4117388-0 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Prüftechnik (DE-588)4047610-8 gnd |
| subject_GND | (DE-588)4055072-2 (DE-588)4059549-3 (DE-588)4117388-0 (DE-588)4027242-4 (DE-588)4047610-8 |
| title | Hierarchical modeling for VLSI circuit testing |
| title_auth | Hierarchical modeling for VLSI circuit testing |
| title_exact_search | Hierarchical modeling for VLSI circuit testing |
| title_full | Hierarchical modeling for VLSI circuit testing by Debashis Bhattacharya and John P. Hayes |
| title_fullStr | Hierarchical modeling for VLSI circuit testing by Debashis Bhattacharya and John P. Hayes |
| title_full_unstemmed | Hierarchical modeling for VLSI circuit testing by Debashis Bhattacharya and John P. Hayes |
| title_short | Hierarchical modeling for VLSI circuit testing |
| title_sort | hierarchical modeling for vlsi circuit testing |
| topic | Circuit intégré Circuits intégrés à très grande échelle ram VLSI Integrated circuits Very large scale integration Computer simulation Integrated circuits Very large scale integration Testing Simulation (DE-588)4055072-2 gnd Test (DE-588)4059549-3 gnd VLSI (DE-588)4117388-0 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Prüftechnik (DE-588)4047610-8 gnd |
| topic_facet | Circuit intégré Circuits intégrés à très grande échelle VLSI Integrated circuits Very large scale integration Computer simulation Integrated circuits Very large scale integration Testing Simulation Test Integrierte Schaltung Prüftechnik |
| volume_link | (DE-604)BV023545171 |
| work_keys_str_mv | AT bhattacharyadebashis hierarchicalmodelingforvlsicircuittesting AT hayesjohnp hierarchicalmodelingforvlsicircuittesting |