Multicomputer networks: message-based parallel processing
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | Undetermined |
| Veröffentlicht: |
Cambridge, Mass. u.a.
MIT Pr.
1988
|
| Ausgabe: | 2. print. |
| Schriftenreihe: | MIT Press series in scientific computation.
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | 380 S. graph. Darst. |
| ISBN: | 0262181290 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV003583755 | ||
| 003 | DE-604 | ||
| 005 | 20140828 | ||
| 007 | t | ||
| 008 | 900725s1988 d||| |||| 00||| und d | ||
| 020 | |a 0262181290 |9 0-262-18129-0 | ||
| 035 | |a (OCoLC)256036636 | ||
| 035 | |a (DE-599)BVBBV003583755 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | |a und | ||
| 049 | |a DE-384 |a DE-83 |a DE-188 | ||
| 084 | |a ST 151 |0 (DE-625)143595: |2 rvk | ||
| 084 | |a ST 200 |0 (DE-625)143611: |2 rvk | ||
| 100 | 1 | |a Reed, Daniel A. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Multicomputer networks |b message-based parallel processing |c Daniel A. Reed and Richard M. Fujimoto |
| 250 | |a 2. print. | ||
| 264 | 1 | |a Cambridge, Mass. u.a. |b MIT Pr. |c 1988 | |
| 300 | |a 380 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a MIT Press series in scientific computation. | |
| 650 | 0 | 7 | |a Parallelrechner |0 (DE-588)4173280-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Mathematisches Modell |0 (DE-588)4114528-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Rechnernetz |0 (DE-588)4070085-9 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Parallelverarbeitung |0 (DE-588)4075860-6 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Parallelrechner |0 (DE-588)4173280-7 |D s |
| 689 | 0 | 1 | |a Mathematisches Modell |0 (DE-588)4114528-8 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Rechnernetz |0 (DE-588)4070085-9 |D s |
| 689 | 1 | 1 | |a Parallelverarbeitung |0 (DE-588)4075860-6 |D s |
| 689 | 1 | |8 1\p |5 DE-604 | |
| 700 | 1 | |a Fujimoto, Richard M. |e Verfasser |4 aut | |
| 856 | 4 | 2 | |m HEBIS Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002281753&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-002281753 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Datensatz im Suchindex
| _version_ | 1804117933688881152 |
|---|---|
| adam_text | Multicomputer Networks: Message-Based Parallel Processing
Daniel A Reed and Richard M Fujimoto
The MIT Press
Cambridge, Massachusetts
London, England
Contents
Series Foreword xiii
Preface xv
1 Introduction 1
1 1 Multicomputer Networks: A Definition 2
12A Parallel Computer Systems Comparison 5
121 Pipelined Vector Processors 5
122 Shared Memory MIMD Multiprocessors 7
1221 The Sequent Balance 21000 8
1222 Large Scale Multiprocessors 8
123 SIMD Computers 10
124 Systolic Arrays 12
125 Data Flow Computers 13
126 Multicomputer Networks 15
1 3 Multicomputer History 16
131 Early Projects 16
132 The Hypercube Topology 17
133 The Cosmic Cube and Its Descendants 19
1 4 Multicomputer Building Blocks 19
141 The Inmos Transputer 20
142 The Torus Routing Chip 20
1 5 Outline of Text 23
151 Communication Systems 24
152 Multicomputer Operating Systems 25
153 Multicomputer Applications 26
154 Performance of Existing Machines 26
2 Analytic Models of Interconnection Networks 29
2 1 Definitions 30
211 Network Connectivity 31
212 Network Diameter 33
213 Mean Internode Distance 33
Contents
2131 Uniform Message Routing - Symmetric
Interconnections 35
2132 Sphere of Locality Message Routing - Symmetric
Interconnections 36
2133 Decreasing Probability Message Routing - Symmetric
Interconnections 37
2134 Uniform Message Routing - Asymmetric
Interconnections 39
214 Visit Ratios 40
215 Expansion Increments 41
2 2 Single Stage Interconnection Networks 42
2 3 Analyzing the Torus: An Example 46
231 The Binary Hypercube: A Special Case 52
2 4 Analysis of Single Stage Interconnection Networks 52
241 Implications of Network Size 53
242 Expansion Increment Comparison 53
243 Network Connectivity Comparison 56
244 Network Diameter Comparison 56
245 Mean Internode Distance Comparison 56
2 5 Communication Link Visit Ratios 60
251 Feasible Computation Quanta 62
252 Network Selection 66
2 6 Nodes with Limited Communication Bandwidth 68
27A Comparison Based on Rankings 69
2 8 Network Performance at Finite Workloads 69
281 Asymptotic Bound Analysis 70
282 Product Form Queueing Networks 71
283 Balanced Job Bound Analysis 74
2831 Approximate Intersection Points 76
2 9 Summary 77
3 VLSI Constraints and the Optimal Number of Ports 80
3 1 VLSI Constraints 81
3 2 Virtual Cut-Through 82
Contents
3 3 Analytic Studies • 83
331 Assumptions 83
332 Model I: Cluster Nodes 85
3321 Queueing Model 86
3322 Delay 90
3323 Bandwidth 91
333 Model II: Fixed Sized Networks 94
3331 Queueing Model 95
3332 Delay 99
3333 Bandwidth 103
334 Summary of Analytic Results 104
3 4 Simulation Studies 107
341 Assumptions 107
342 The Application Programs 108
3421 Bamwell Filter Program (global SISO, 12 tasks) 111
3422 Block I/O Filter Program (local SISO, 23 tasks) 111
3423 Block State Filter Program (local SISO, 20 tasks) 112
3424 FFT Program (local PIPO, 32 tasks) 113
3425 LU Decomposition (global PIPO, 15 tasks) 114
3426 Artificial Traffic Loads (global PIPO, 12 tasks) 116
3427 Characterization of the Application Programs 116
343 Issues Under Investigation 119
344 Simulation Results on Cluster Node Networks 120
3441 Fully Connected Networks 121
3442 Full-Ring Tree Networks 122
3443 Butterfly Networks 123
3444 Ring Networks 123
3445 Conclusions for Cluster Node Networks 127
345 Simulation Results on Fixed Sized Networks 128
3451 Lattice Topologies 128
3452 Tree Topologies 130
3453 De Bruijn Networks 131
3 5 Summary 134
Contents
4 Communication Paradigms and Hardware Support 138
4 1 Transport Mechanisms 139
42A Virtual Circuit Based Communication System 142
421 Virtual Circuits 142
422 Virtual Channels 143
423 Translation Tables 144
424 Switch Architecture 145
4 3 Routing 148
4 4 Buffer Management 152
4 5 Flow Control 157
451A Send / Acknowledge Protocol 158
452 Remote Buffer Management 162
4 6 Evaluation of Design Parameters • 164
461 Number of Virtual Channels 164
462 Amount of Buffer Space 165
4621 Buffer Space: Deadlock Considerations 166
4622 Buffer Space: Performance Considerations 169
4 7 Complexity of the Communication Circuitry 172
4 8 Summary • 174
5 Multicomputer Network Operating Systems 177
5 1 Overview 179
5 2 Scheduling Static Tasks 183
521A Formal Model of Static Task Scheduling 183
522 Static Scheduling Via Integer Programming 186
523 Static Scheduling Via Clustering 188
5231 Initialization 190
5232 Iterative Task Assignment 190
524 Static Scheduling Via Simulated Annealing 192
5241A Sample Problem 194
5242 Minimization Criterion 196
5243 Algorithm Implementation 197
5244 Experiments 197
Contents
5245 General Observations 198
5 3 Scheduling Dynamic Tasks 198
531A Feasibility Study of Dynamic Scheduling 200
5311 Task Precedence Graphs 201
5312 Simulation Methodology 202
5313 Simulation Experiments 205
5314 General Observations 212
532 Dynamic Scheduling Via Gradient Planes 213
5321 Creating Gradient Planes 214
5322 The Gradient Plane Algorithm 214
5323 Simulation Studies 217
5324 General Observations 222
533 Dynamic Scheduling Via Waves 224
5331 Management Hierarchies 224
5332 Wave Scheduling Algorithm 225
5333 Analysis of Wave Scheduling 228
5 4 Fault Tolerance 230
541 Recovery Methods 232
542 Summary 234
5 5 Future Directions in Operating Systems 234
6 Applications: Distributed Simulation 239
6 1 Simulation of Discrete Systems 239
611 The Causality Principle 240
612 What is Distributed Simulation? 241
613 Why is Distributed Simulation Hard? 243
614 An Example 245
615 Overview of Distributed Simulation Strategies 247
6 2 The Deadlock Avoidance Approach 248
621 The Selection Phase 252
622 The Computation Phase 252
623 The I/O Phase 252
624 Initialization and Termination 253
Contents
6 3 The Deadlock Detection and Recovery Approach 253
631 The Simulation Phase 253
632 The Dijkstra Scholten Algorithm (DSA) 254
633 The Chandy Misra Algorithm (CMA) 256
634 Deadlock Recovery 258
635 Simulation Using Deadlock Detection 260
6 4 The Time Warp Mechanism 261
641 Assumptions 261
642 Logical Processes 261
643 Error Detection and Roll Back 262
644 Anti-Messages 263
645 Global Virtual Time 264
646 Flow Control 265
647 I/O and Runtime Errors 265
648 Termination Detection 265
6 5 Summary 266
7 Applications: Partial Differential Equations 268
7 1 Solution Techniques 270
7 2 Grid Partitions 273
721 Related Work 274
722 Five Point Stencil 275
7221 Rectangular Partitions 275
7222 Triangular Partitions 276
7223 Hexagonal Partitions 277
723 Nine Point Stencil 278
7231 Rectangular Partitions 279
7232 Triangular Partitions 280
7233 Hexagonal Partitions 280
724 Other Stencils 281
7 3 Computation/Communication Ratios 282
7 4 Optimal Pairs of Stencil and Partition 283
7 5 Performance Models 287
Contents
751 Message Passing Analysis 292
752 Performance Prediction 295
753 Experimental Validation 298
7 6 Summary 303
8 Commercial Hypercubes: A Performance Analysis 305
8 1 Hypercube Architectures 307
811 Intel iPSC 307
8111 Hardware Organization 307
8112 Software Organization 311
812 Ametek System/14 317
8121 Hardware Organization 317
8122 Software Organization 319
813 JPL Mark-Ill 324
8131 Hardware Organization 325
8132 Software Organization 327
814 Ncube/ten 328
8141 Hardware Organization 328
8142 Software Organization 330
815 FPS T Series 330
8151 Hardware Organization 331
8152 Software Organization 334
8 2 Hypercube Performance Analysis 335
821 Performance Study I (Intel, Ametek, JPL) 335
8211 Test Environment 336
8212 Processor Benchmarks 338
8213 Simple Communication Benchmarks 341
8214 Synthetic Communication Benchmarks 347
8215 Temporal Locality 348
8216 Spatial Locality 349
8217 Experimental Results 350
822 Performance Study II (FPS T Series) 352
8221 Processor Benchmarks 353
Contents
8222 Communication Benchmarks 356
8223 FPS T Series System Balance 359
823 Performance Study III (Intel iPSC/VX) 361
8 3 Hypercube System Comparisons 362
831 Hardware 363
832 Software 364
833 Summary 370
8 4 Future Directions 370
Index 378
|
| any_adam_object | 1 |
| author | Reed, Daniel A. Fujimoto, Richard M. |
| author_facet | Reed, Daniel A. Fujimoto, Richard M. |
| author_role | aut aut |
| author_sort | Reed, Daniel A. |
| author_variant | d a r da dar r m f rm rmf |
| building | Verbundindex |
| bvnumber | BV003583755 |
| classification_rvk | ST 151 ST 200 |
| ctrlnum | (OCoLC)256036636 (DE-599)BVBBV003583755 |
| discipline | Informatik |
| edition | 2. print. |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01877nam a2200457 c 4500</leader><controlfield tag="001">BV003583755</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20140828 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">900725s1988 d||| |||| 00||| und d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0262181290</subfield><subfield code="9">0-262-18129-0</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)256036636</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV003583755</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">und</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-384</subfield><subfield code="a">DE-83</subfield><subfield code="a">DE-188</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 151</subfield><subfield code="0">(DE-625)143595:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 200</subfield><subfield code="0">(DE-625)143611:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Reed, Daniel A.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Multicomputer networks</subfield><subfield code="b">message-based parallel processing</subfield><subfield code="c">Daniel A. Reed and Richard M. Fujimoto</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">2. print.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Cambridge, Mass. u.a.</subfield><subfield code="b">MIT Pr.</subfield><subfield code="c">1988</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">380 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">MIT Press series in scientific computation.</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Parallelrechner</subfield><subfield code="0">(DE-588)4173280-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Mathematisches Modell</subfield><subfield code="0">(DE-588)4114528-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Rechnernetz</subfield><subfield code="0">(DE-588)4070085-9</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Parallelverarbeitung</subfield><subfield code="0">(DE-588)4075860-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Parallelrechner</subfield><subfield code="0">(DE-588)4173280-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Mathematisches Modell</subfield><subfield code="0">(DE-588)4114528-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Rechnernetz</subfield><subfield code="0">(DE-588)4070085-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Parallelverarbeitung</subfield><subfield code="0">(DE-588)4075860-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Fujimoto, Richard M.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">HEBIS Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002281753&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-002281753</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield></record></collection> |
| id | DE-604.BV003583755 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T16:02:17Z |
| institution | BVB |
| isbn | 0262181290 |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-002281753 |
| oclc_num | 256036636 |
| open_access_boolean | |
| owner | DE-384 DE-83 DE-188 |
| owner_facet | DE-384 DE-83 DE-188 |
| physical | 380 S. graph. Darst. |
| publishDate | 1988 |
| publishDateSearch | 1988 |
| publishDateSort | 1988 |
| publisher | MIT Pr. |
| record_format | marc |
| series2 | MIT Press series in scientific computation. |
| spelling | Reed, Daniel A. Verfasser aut Multicomputer networks message-based parallel processing Daniel A. Reed and Richard M. Fujimoto 2. print. Cambridge, Mass. u.a. MIT Pr. 1988 380 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier MIT Press series in scientific computation. Parallelrechner (DE-588)4173280-7 gnd rswk-swf Mathematisches Modell (DE-588)4114528-8 gnd rswk-swf Rechnernetz (DE-588)4070085-9 gnd rswk-swf Parallelverarbeitung (DE-588)4075860-6 gnd rswk-swf Parallelrechner (DE-588)4173280-7 s Mathematisches Modell (DE-588)4114528-8 s DE-604 Rechnernetz (DE-588)4070085-9 s Parallelverarbeitung (DE-588)4075860-6 s 1\p DE-604 Fujimoto, Richard M. Verfasser aut HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002281753&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Reed, Daniel A. Fujimoto, Richard M. Multicomputer networks message-based parallel processing Parallelrechner (DE-588)4173280-7 gnd Mathematisches Modell (DE-588)4114528-8 gnd Rechnernetz (DE-588)4070085-9 gnd Parallelverarbeitung (DE-588)4075860-6 gnd |
| subject_GND | (DE-588)4173280-7 (DE-588)4114528-8 (DE-588)4070085-9 (DE-588)4075860-6 |
| title | Multicomputer networks message-based parallel processing |
| title_auth | Multicomputer networks message-based parallel processing |
| title_exact_search | Multicomputer networks message-based parallel processing |
| title_full | Multicomputer networks message-based parallel processing Daniel A. Reed and Richard M. Fujimoto |
| title_fullStr | Multicomputer networks message-based parallel processing Daniel A. Reed and Richard M. Fujimoto |
| title_full_unstemmed | Multicomputer networks message-based parallel processing Daniel A. Reed and Richard M. Fujimoto |
| title_short | Multicomputer networks |
| title_sort | multicomputer networks message based parallel processing |
| title_sub | message-based parallel processing |
| topic | Parallelrechner (DE-588)4173280-7 gnd Mathematisches Modell (DE-588)4114528-8 gnd Rechnernetz (DE-588)4070085-9 gnd Parallelverarbeitung (DE-588)4075860-6 gnd |
| topic_facet | Parallelrechner Mathematisches Modell Rechnernetz Parallelverarbeitung |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=002281753&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT reeddaniela multicomputernetworksmessagebasedparallelprocessing AT fujimotorichardm multicomputernetworksmessagebasedparallelprocessing |