Synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Mikrofilm Buch |
| Sprache: | English |
| Veröffentlicht: |
1979
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| Ausgabe: | [Mikrofiche-Ausg.] |
| Schlagworte: | |
| Beschreibung: | Includes bibliographical references (leaves 162-166) |
| Beschreibung: | V, 166 leaves graph. Darst. |
Internformat
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| 100 | 1 | |a Wu, Kwok-Wai |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment |c by Kwok-Wai Wu |
| 250 | |a [Mikrofiche-Ausg.] | ||
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| 338 | |b he |2 rdacarrier | ||
| 500 | |a Includes bibliographical references (leaves 162-166) | ||
| 502 | |a Austin, Tex., Univ., Diss., 1979 | ||
| 533 | |a Mikroform-Ausgabe |b Ann Arbor, Mich. |c Univ. Microfilms Internat. |d 1980 |e 2 Mikrofiches |n Mikrofiche-Ausg.: |7 s1980 | ||
| 650 | 4 | |a Logic design / Data processing | |
| 650 | 4 | |a Digital integrated circuits | |
| 650 | 4 | |a Digital computer simulation | |
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Digital computer simulation | |
| 650 | 4 | |a Digital integrated circuits | |
| 650 | 4 | |a Logic design |x Data processing | |
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 776 | 0 | 8 | |i Reproduktion von |a Wu, Kwok-Wai |t Synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment |d 1979 |
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Datensatz im Suchindex
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| author | Wu, Kwok-Wai |
| author_facet | Wu, Kwok-Wai |
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| edition | [Mikrofiche-Ausg.] |
| format | Thesis Microfilm Book |
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| illustrated | Illustrated |
| indexdate | 2024-07-09T22:03:41Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-018612343 |
| oclc_num | 6777022 |
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| owner | DE-706 |
| owner_facet | DE-706 |
| physical | V, 166 leaves graph. Darst. |
| publishDate | 1979 |
| publishDateSearch | 1979 |
| publishDateSort | 1979 |
| record_format | marc |
| spelling | Wu, Kwok-Wai Verfasser aut Synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment by Kwok-Wai Wu [Mikrofiche-Ausg.] 1979 V, 166 leaves graph. Darst. txt rdacontent h rdamedia he rdacarrier Includes bibliographical references (leaves 162-166) Austin, Tex., Univ., Diss., 1979 Mikroform-Ausgabe Ann Arbor, Mich. Univ. Microfilms Internat. 1980 2 Mikrofiches Mikrofiche-Ausg.: s1980 Logic design / Data processing Digital integrated circuits Digital computer simulation Datenverarbeitung Logic design Data processing (DE-588)4113937-9 Hochschulschrift gnd-content Reproduktion von Wu, Kwok-Wai Synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment 1979 |
| spellingShingle | Wu, Kwok-Wai Synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment Logic design / Data processing Digital integrated circuits Digital computer simulation Datenverarbeitung Logic design Data processing |
| subject_GND | (DE-588)4113937-9 |
| title | Synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment |
| title_auth | Synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment |
| title_exact_search | Synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment |
| title_full | Synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment by Kwok-Wai Wu |
| title_fullStr | Synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment by Kwok-Wai Wu |
| title_full_unstemmed | Synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment by Kwok-Wai Wu |
| title_short | Synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment |
| title_sort | synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment |
| topic | Logic design / Data processing Digital integrated circuits Digital computer simulation Datenverarbeitung Logic design Data processing |
| topic_facet | Logic design / Data processing Digital integrated circuits Digital computer simulation Datenverarbeitung Logic design Data processing Hochschulschrift |
| work_keys_str_mv | AT wukwokwai synthesisofaccurateandefficientfunctionalmodellingtechniquesforperformingdesignverificationofverylargescaleintegrateddigitalcircuitsandsystemsinahierarchicaldigitallogicsimulationenvironment |