Programming for hybrid multi/manycore MPP systems:
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Boca Raton
CRC Press, Taylor & Francis Group
[2018]
|
| Series: | Chapman & Hall/CRC computational science series
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis Klappentext |
| Item Description: | Includes index |
| Physical Description: | xxxv, 305 pages illustrations 23 cm |
| ISBN: | 9781439873717 |
Staff View
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Record in the Search Index
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|---|---|
| adam_text | Contents
Preface
About the Authors
List of Figures
List of Tables
List of Excerpts
Pj
Chapter 1 ■ Introduction 1
1.1 INTRODUCTION 1
1.2 CHAPTER OVERVIEWS 3
Chapter 2 ■ Determining an Exaflop Strategy 7
2.1 FOREWORD BY JOHN LEVESQUE 7
2.2 INTRODUCTION 8
2.3 LOOKING AT THE APPLICATION 9
2.4 DEGREE OF HYBRIDIZATION REQUIRED 13
2.5 DECOMPOSITION AND I/O 15
2.6 PARALLEL AND VECTOR LENGTHS 15
2.7 PRODUCTIVITY AND PERFORMANCE PORTABILITY 15
2.8 CONCLUSION 19
2.9 EXERCISES 19
Chapter 3 ■ Target Hybrid Multi/Manycore System 21
3.1 FOREWORD BY JOHN LEVESQUE 21
xi
xii ■ Contents
3.2 UNDERSTANDING THE ARCHITECTURE 22
3.3 CACHE ARCHITECTURES 23
3.3.1 Xeon Cache 24
3.3.2 NVIDIA GPU Cache 25
3.4 MEMORY HIERARCHY 25
3.4.1 Knight’s Landing Cache 27
3.5 KNL CLUSTERING MODES 28
3.6 KNL MCDRAM MODES 33
3.7 IMPORTANCE OF VECTORIZATION 38
3.8 ALIGNMENT FOR VECTORIZATION 40
3.9 EXERCISES 40
Chapter 4 ■ How Compilers Optimize Programs 43
4.1 FOREWORD BY JOHN LEVESQUE 43
4.2 INTRODUCTION 45
4.3 MEMORY ALLOCATION 45
4.4 MEMORY ALIGNMENT 47
4.5 COMMENT-LINE DIRECTIVE 48
4.6 INTERPROCEDURAL ANALYSIS 49
4.7 COMPILER SWITCHES 49
4.8 FORTRAN 2003 AND INEFFICIENCIES 50
4.8.1 Array Syntax 51
4.8.2 Use Optimized Libraries 53
4.8.3 Passing Array Sections 53
4.8.4 Using Modules for Local Variables 54
4.8.5 Derived Types 54
4.9 C/C++AND INEFFICIENCIES 55
4.10 COMPILER SCALAR OPTIMIZATIONS 61
4.10.1 Strength Reduction 61
4.10.2 Avoiding Floating Point Exponents 63
4.10.3 Common Subexpression Elimination 64
4.11 EXERCISES 65
Chapter 5 ■ Gathering Runtime Statistics for Optimizing 67
5.1 FOREWORD BY JOHN LEVESQUE
67
Contents ■ xiii
5.2 INTRODUCTION 68
5.3 WHAT S IMPORTANT TO PROFILE 69
5.3.1 Profiling NAS BT 69
5.3.2 Profiling VH1 74
5.4 CONCLUSION 76
5.5 EXERCISES 77
Chapter 6 ■ Utilization of Available Memory Bandwidth 79
6.1 FOREWORD BY JOHN LEVESQUE 79
6.2 INTRODUCTION 80
6.3 IMPORTANCE OF CACHE OPTIMIZATION 80
6.4 VARIABLE ANALYSIS IN MULTIPLE LOOPS 81
6.5 OPTIMIZING FOR THE CACHE HIERARCHY 84
6.6 COMBINING MULTIPLE LOOPS 93
6.7 CONCLUSION 96
6.8 EXERCISES 96
Chapter 7 ■ Vectorization 97
7.1 FOREWORD BY JOHN LEVESQUE 97
7.2 INTRODUCTION 98
7.3 VECTORIZATION INHIBITORS 99
7.4 VECTORIZATION REJECTION FROM INEFFICIENCIES 101
7.4.1 Access Modes and Computational Intensity 101
7.4.2 Conditionals 104
7.5 STRIDING VERSUS CONTIGUOUS ACCESSING 107
7.6 WRAP-AROUND SCALAR 111
7.7 LOOPS SAVING MAXIMA AND MINIMA 114
7.8 MULTINESTED LOOP STRUCTURES 116
7.9 THERE S MATMUL AND THEN THERE S MATMUL 119
7.10 DECISION PROCESSES IN LOOPS 122
7.10.1 Loop-Independent Conditionals 123
7.10.2 Conditionals Directly Testing Indicies 125
7.10.3 Loop-Dependent Conditionals 130
7.10.4 Conditionals Causing Early Loop Exit 132
7.11 HANDLING FUNCTION CALLS WITHIN LOOPS 134
xiv ■ Contents
7.12 RANK EXPANSION 139
7.13 OUTER LOOP VECTOR1ZATION 143
7.14 EXERCISES 144
Chapter 8 ■ Hybridization of an Application 147
8.1 FOREWORD BY JOHN LEVESQUE 147
8.2 INTRODUCTION 147
8.3 THE NODE S NUMA ARCHITECTURE 148
8.4 FIRST TOUCH IN THE HIMENO BENCHMARK 149
8.5 IDENTIFYING WHICH LOOPS TO THREAD 153
8.6 SPMDOPENMP 158
8.7 EXERCISES 167
Chapter 9 ■ Porting Entire Applications 169
9.1 FOREWORD BY JOHN LEVESQUE 169
9.2 INTRODUCTION 170
9.3 SPEC OPENMP BENCHMARKS 170
9.3.1 WUPWISE 170
9.3.2 MGRID 175
9.3.3 GALGEL 177
9.3.4 APSI 179
9.3.5 FMA3D 182
9.3.6 AMMP 184
9.3.7 SWIM 190
9.3.8 APPLU 192
9.3.9 EQUAKE 194
9.3.10 ART 201
9.4 NASA PARALLEL BENCHMARK (NPB) BT 208
9.5 REFACTORING VH-1 218
9.6 REFACTORING LESLIE3D 223
9.7 REFACTORING S3D - 2016 PRODUCTION VERSION 226
9.8 PERFORMANCE PORTABLE - S3D ON TITAN 230
9.9 EXERCISES 241
Contents ■ xv
Chapter 10 Future Hardware Advancements 243
10.1 INTRODUCTION 243
10.2 FUTURE X86 CPUS 244
10.2.1 Intel Sky lake 244
10.2.2 AMD Zen 244
10.3 FUTURE ARM CPUS 245
10.3.1 Scalable Vector Extension 245
10.3.2 Broadcom Vulcan 248
10.3.3 Cavium Thunder X 249
10.3.4 Fujitsu Post-K 249
10.3.5 Qualcomm Centriq 249
10.4 FUTURE MEMORY TECHNOLOGIES 250
10.4.1 Die-Stacking Technologies 250
10.4.2 Compute Near Data 251
10.5 FUTURE HARDWARE CONCLUSIONS 252
10.5.1 Increased Thread Counts 252
10.5.2 Wider Vectors 252
10.5.3 Increasingly Complex Memory Hierarchies 254
Appendix A ■ Supercomputer Cache Architectures 255
A.1 ASSOCIATIVITY 255
Appendix B ■ The Translation Look-Aside Buffer 261
B.1 INTRODUCTION TO THE TLB 261
Appendix C ■ Command Line Options and Compiler Direc-
tives 263
C.1 COMMAND LINE OPTIONS AND COMPILER DIRECTIVES 263
Appendix D ■ Previously Used Optimizations 265
D.1 LOOP REORDERING 265
D.2 INDEX REORDERING 266
xvi ■ Contents
D.3 LOOP UNROLLING 266
D.4 LOOP FISSION 266
D.5 SCALAR PROMOTION 266
D.6 REMOVAL OF LOOP-INDEPENDENT IFS 267
D.7 USE OF INTR1NSICS TO REMOVE IFS 267
D.8 STRIP MINING 267
D.9 SUBROUTINE INLINING 267
D.10 PULLING LOOPS INTO SUBROUTINES 267
D.11 CACHE BLOCKING 268
D.12 LOOP FUSION 268
D.13 OUTER LOOP VECTORIZATION 268
Appendix E ■ I/O Optimization______________________269
E.1 INTRODUCTION 269
E.2 I/O STRATEGIES 269
E.2.1 Spokesperson 269
E.2.2 Multiple Writers - Multiple Files 270
E.2.3 Collective I/O to Single or Multiple Files 270
E.3 LUSTRE MECHANICS 270
Appendix F ■ Terminology________________________________273
F.1 SELECTED DEFINITIONS
273
Appendix G ■ 12-Step Process
277
G.1 INTRODUCTION 277
G.2 PROCESS 277
Bibliography 279
Crypto 283
Index 285
COMPUTER SCIENCE ENGINEERING
Programming for Hybrid Multi/Manycore MPP Systems
Ask not what your compiler can do for you, ask what you can do for your compiler.
—John Levesque, Director of Cray’s Supercomputing Centers of Excellence
The next decade of computationally intense computing lies with more power-
ful multi/manycore nodes where processors share a large memory space. These
nodes will be the building block for systems that range from a single node
workstation up to systems approaching the exaflop regime. The node itself will
consist of 10’s to 100’s of MIMD (multiple instruction, multiple data) processing
units with SIMD (single instruction, multiple data) parallel instructions. Since
a standard, affordable memory architecture will not be able to supply the band-
width required by these cores, new memory organizations will be introduced.
These new node architectures will represent a significant challenge to application
developers.
Programming for Hybrid Multi/Manycore MPP Systems attempts to briefly
describe the current state-of-the-art in programming these systems and pro-
poses an approach for developing a performance-portable application that can
effectively utilize all of these systems from a single application. The book starts
with a strategy for optimizing an application for multi/manycore architectures.
It then looks at the three typical architectures, covering their advantages and
disadvantages.
The next section of the book explores the other important component of the
target, the compiler. The compiler will ultimately convert the input language to
executable code on the target, and the book explores how to make the compiler
do what we want. The book then talks about gathering runtime statistics from
running the application on the important problem sets previously discussed.
How best to utilize available memory bandwidth and virtualization are covered
next, along with hybridization of a program. The last part of the book includes
several major applications, and examines future hardware advancements, and
how the application developer may prepare for those advancements.
CRC Press
Taylor Si Francis Group
an Informa business
6000 Broken Sound Parkway, NW
Suite 300, Boca Raton, FL 33487
711 Third Avenue
New York, NY 10017
2 Park Square, Milton Park
Abingdon, Oxon OX14 4RN, UK
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ISBN: TVÖ-l-MBTfl-VB?!-?
I TDDDD
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www.crcpress.com
|
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| spelling | Levesque, John M. Verfasser aut Programming for hybrid multi/manycore MPP systems John Levesque, Aaron Vose Boca Raton CRC Press, Taylor & Francis Group [2018] xxxv, 305 pages illustrations 23 cm txt rdacontent n rdamedia nc rdacarrier Chapman & Hall/CRC computational science series Includes index Parallel programming (Computer science) Multiprocessors Programming Coprocessors Programming Parallelrechner (DE-588)4173280-7 gnd rswk-swf Mehrkernprozessor (DE-588)7598578-0 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 s Mehrkernprozessor (DE-588)7598578-0 s Parallelrechner (DE-588)4173280-7 s DE-604 Vose, Aaron Verfasser aut Digitalisierung UB Bayreuth - ADAM Catalogue Enrichment application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=030320820&sequence=000003&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis Digitalisierung UB Bayreuth - ADAM Catalogue Enrichment application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=030320820&sequence=000004&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA Klappentext |
| spellingShingle | Levesque, John M. Vose, Aaron Programming for hybrid multi/manycore MPP systems Parallel programming (Computer science) Multiprocessors Programming Coprocessors Programming Parallelrechner (DE-588)4173280-7 gnd Mehrkernprozessor (DE-588)7598578-0 gnd Computerarchitektur (DE-588)4048717-9 gnd |
| subject_GND | (DE-588)4173280-7 (DE-588)7598578-0 (DE-588)4048717-9 |
| title | Programming for hybrid multi/manycore MPP systems |
| title_auth | Programming for hybrid multi/manycore MPP systems |
| title_exact_search | Programming for hybrid multi/manycore MPP systems |
| title_full | Programming for hybrid multi/manycore MPP systems John Levesque, Aaron Vose |
| title_fullStr | Programming for hybrid multi/manycore MPP systems John Levesque, Aaron Vose |
| title_full_unstemmed | Programming for hybrid multi/manycore MPP systems John Levesque, Aaron Vose |
| title_short | Programming for hybrid multi/manycore MPP systems |
| title_sort | programming for hybrid multi manycore mpp systems |
| topic | Parallel programming (Computer science) Multiprocessors Programming Coprocessors Programming Parallelrechner (DE-588)4173280-7 gnd Mehrkernprozessor (DE-588)7598578-0 gnd Computerarchitektur (DE-588)4048717-9 gnd |
| topic_facet | Parallel programming (Computer science) Multiprocessors Programming Coprocessors Programming Parallelrechner Mehrkernprozessor Computerarchitektur |
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