Internformat
MARC
| LEADER | 00000nam a22000001c 4500 | ||
|---|---|---|---|
| 001 | BV047852359 | ||
| 003 | DE-604 | ||
| 005 | 20220224 | ||
| 007 | t | ||
| 008 | 220223s2022 |||| 00||| eng d | ||
| 020 | |a 9781119778042 |c Hardcover |9 978-1-119-77804-2 | ||
| 035 | |a (OCoLC)1302313248 | ||
| 035 | |a (DE-599)BVBBV047852359 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-1043 | ||
| 084 | |a ZN 4950 |0 (DE-625)157424: |2 rvk | ||
| 100 | 1 | |a Tripathi, Suman Lata |e Verfasser |0 (DE-588)1240855079 |4 aut | |
| 245 | 1 | 0 | |a Digital VLSI Design and Simulation with Verilog |c Dr. Suman Lata Tripathi, Dr. Sobhit Saxena, Dr. Sanjeet Kumar Sinha, Dr. Govind Singh Patel |
| 250 | |a 1st edition | ||
| 264 | 1 | |a Hoboken |b Wiley |c 2022 | |
| 300 | |a XIV, 206 Seiten | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 1 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Saxena, Sobhit |e Verfasser |4 aut | |
| 700 | 1 | |a Sinha, Sanjeet Kumar |e Verfasser |4 aut | |
| 700 | 1 | |a Patel, Govind Singh |e Verfasser |4 aut | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-033235192 | ||
Datensatz im Suchindex
| _version_ | 1804183417364938752 |
|---|---|
| adam_txt | |
| any_adam_object | |
| any_adam_object_boolean | |
| author | Tripathi, Suman Lata Saxena, Sobhit Sinha, Sanjeet Kumar Patel, Govind Singh |
| author_GND | (DE-588)1240855079 |
| author_facet | Tripathi, Suman Lata Saxena, Sobhit Sinha, Sanjeet Kumar Patel, Govind Singh |
| author_role | aut aut aut aut |
| author_sort | Tripathi, Suman Lata |
| author_variant | s l t sl slt s s ss s k s sk sks g s p gs gsp |
| building | Verbundindex |
| bvnumber | BV047852359 |
| classification_rvk | ZN 4950 |
| ctrlnum | (OCoLC)1302313248 (DE-599)BVBBV047852359 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 1st edition |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01269nam a22003731c 4500</leader><controlfield tag="001">BV047852359</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20220224 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">220223s2022 |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781119778042</subfield><subfield code="c">Hardcover</subfield><subfield code="9">978-1-119-77804-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1302313248</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV047852359</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-1043</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4950</subfield><subfield code="0">(DE-625)157424:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Tripathi, Suman Lata</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)1240855079</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Digital VLSI Design and Simulation with Verilog</subfield><subfield code="c">Dr. Suman Lata Tripathi, Dr. Sobhit Saxena, Dr. Sanjeet Kumar Sinha, Dr. Govind Singh Patel</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">1st edition</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Hoboken</subfield><subfield code="b">Wiley</subfield><subfield code="c">2022</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XIV, 206 Seiten</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Saxena, Sobhit</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Sinha, Sanjeet Kumar</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Patel, Govind Singh</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-033235192</subfield></datafield></record></collection> |
| id | DE-604.BV047852359 |
| illustrated | Not Illustrated |
| index_date | 2024-07-03T19:15:02Z |
| indexdate | 2024-07-10T09:23:07Z |
| institution | BVB |
| isbn | 9781119778042 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-033235192 |
| oclc_num | 1302313248 |
| open_access_boolean | |
| owner | DE-1043 |
| owner_facet | DE-1043 |
| physical | XIV, 206 Seiten |
| publishDate | 2022 |
| publishDateSearch | 2022 |
| publishDateSort | 2022 |
| publisher | Wiley |
| record_format | marc |
| spelling | Tripathi, Suman Lata Verfasser (DE-588)1240855079 aut Digital VLSI Design and Simulation with Verilog Dr. Suman Lata Tripathi, Dr. Sobhit Saxena, Dr. Sanjeet Kumar Sinha, Dr. Govind Singh Patel 1st edition Hoboken Wiley 2022 XIV, 206 Seiten txt rdacontent n rdamedia nc rdacarrier VLSI (DE-588)4117388-0 gnd rswk-swf VERILOG (DE-588)4268385-3 gnd rswk-swf VLSI (DE-588)4117388-0 s VERILOG (DE-588)4268385-3 s DE-604 Saxena, Sobhit Verfasser aut Sinha, Sanjeet Kumar Verfasser aut Patel, Govind Singh Verfasser aut |
| spellingShingle | Tripathi, Suman Lata Saxena, Sobhit Sinha, Sanjeet Kumar Patel, Govind Singh Digital VLSI Design and Simulation with Verilog VLSI (DE-588)4117388-0 gnd VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4268385-3 |
| title | Digital VLSI Design and Simulation with Verilog |
| title_auth | Digital VLSI Design and Simulation with Verilog |
| title_exact_search | Digital VLSI Design and Simulation with Verilog |
| title_exact_search_txtP | Digital VLSI Design and Simulation with Verilog |
| title_full | Digital VLSI Design and Simulation with Verilog Dr. Suman Lata Tripathi, Dr. Sobhit Saxena, Dr. Sanjeet Kumar Sinha, Dr. Govind Singh Patel |
| title_fullStr | Digital VLSI Design and Simulation with Verilog Dr. Suman Lata Tripathi, Dr. Sobhit Saxena, Dr. Sanjeet Kumar Sinha, Dr. Govind Singh Patel |
| title_full_unstemmed | Digital VLSI Design and Simulation with Verilog Dr. Suman Lata Tripathi, Dr. Sobhit Saxena, Dr. Sanjeet Kumar Sinha, Dr. Govind Singh Patel |
| title_short | Digital VLSI Design and Simulation with Verilog |
| title_sort | digital vlsi design and simulation with verilog |
| topic | VLSI (DE-588)4117388-0 gnd VERILOG (DE-588)4268385-3 gnd |
| topic_facet | VLSI VERILOG |
| work_keys_str_mv | AT tripathisumanlata digitalvlsidesignandsimulationwithverilog AT saxenasobhit digitalvlsidesignandsimulationwithverilog AT sinhasanjeetkumar digitalvlsidesignandsimulationwithverilog AT patelgovindsingh digitalvlsidesignandsimulationwithverilog |