Fault simulation on parallel inference machines:
Abstract: "This paper describes a method of fault simulation for parallel processors. The proposed method is based on Time Warp for good simulation and Single Fault Propagation for fault simulation. These methods, however, are modified for efficient parallel execution, removing the barrier betw...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | Japanese English |
| Veröffentlicht: |
Tokyo, Japan
1992
|
| Schriftenreihe: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum
1197 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "This paper describes a method of fault simulation for parallel processors. The proposed method is based on Time Warp for good simulation and Single Fault Propagation for fault simulation. These methods, however, are modified for efficient parallel execution, removing the barrier between good and fault simulation, and simulating multiple faulty circuits in parallel. Preliminary performance evaluation results on parallel inference machines, Multi-PSI and PIM/m, show good efficiency of our method, about 6 fold speedup on 9 processors even for a small circuit." |
| Beschreibung: | 7 S. |
Internformat
MARC
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| 100 | 1 | |a Nakashima, Hiroshi |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Fault simulation on parallel inference machines |c H. Nakashima & R. Satoh |
| 264 | 1 | |a Tokyo, Japan |c 1992 | |
| 300 | |a 7 S. | ||
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| 490 | 1 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum |v 1197 | |
| 520 | 3 | |a Abstract: "This paper describes a method of fault simulation for parallel processors. The proposed method is based on Time Warp for good simulation and Single Fault Propagation for fault simulation. These methods, however, are modified for efficient parallel execution, removing the barrier between good and fault simulation, and simulating multiple faulty circuits in parallel. Preliminary performance evaluation results on parallel inference machines, Multi-PSI and PIM/m, show good efficiency of our method, about 6 fold speedup on 9 processors even for a small circuit." | |
| 650 | 4 | |a Fault-tolerant computing | |
| 650 | 4 | |a Fifth generation computers | |
| 650 | 4 | |a Parallel processing (Electronic computers) | |
| 700 | 1 | |a Satoh, Reiko |e Verfasser |4 aut | |
| 830 | 0 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum |v 1197 |w (DE-604)BV010943497 |9 1197 | |
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Datensatz im Suchindex
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| any_adam_object | |
| author | Nakashima, Hiroshi Satoh, Reiko |
| author_facet | Nakashima, Hiroshi Satoh, Reiko |
| author_role | aut aut |
| author_sort | Nakashima, Hiroshi |
| author_variant | h n hn r s rs |
| building | Verbundindex |
| bvnumber | BV010976405 |
| ctrlnum | (OCoLC)27468839 (DE-599)BVBBV010976405 |
| format | Book |
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| id | DE-604.BV010976405 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T18:01:59Z |
| institution | BVB |
| language | Japanese English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007345199 |
| oclc_num | 27468839 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 7 S. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum |
| spelling | Nakashima, Hiroshi Verfasser aut Fault simulation on parallel inference machines H. Nakashima & R. Satoh Tokyo, Japan 1992 7 S. txt rdacontent n rdamedia nc rdacarrier Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum 1197 Abstract: "This paper describes a method of fault simulation for parallel processors. The proposed method is based on Time Warp for good simulation and Single Fault Propagation for fault simulation. These methods, however, are modified for efficient parallel execution, removing the barrier between good and fault simulation, and simulating multiple faulty circuits in parallel. Preliminary performance evaluation results on parallel inference machines, Multi-PSI and PIM/m, show good efficiency of our method, about 6 fold speedup on 9 processors even for a small circuit." Fault-tolerant computing Fifth generation computers Parallel processing (Electronic computers) Satoh, Reiko Verfasser aut Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum 1197 (DE-604)BV010943497 1197 |
| spellingShingle | Nakashima, Hiroshi Satoh, Reiko Fault simulation on parallel inference machines Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum Fault-tolerant computing Fifth generation computers Parallel processing (Electronic computers) |
| title | Fault simulation on parallel inference machines |
| title_auth | Fault simulation on parallel inference machines |
| title_exact_search | Fault simulation on parallel inference machines |
| title_full | Fault simulation on parallel inference machines H. Nakashima & R. Satoh |
| title_fullStr | Fault simulation on parallel inference machines H. Nakashima & R. Satoh |
| title_full_unstemmed | Fault simulation on parallel inference machines H. Nakashima & R. Satoh |
| title_short | Fault simulation on parallel inference machines |
| title_sort | fault simulation on parallel inference machines |
| topic | Fault-tolerant computing Fifth generation computers Parallel processing (Electronic computers) |
| topic_facet | Fault-tolerant computing Fifth generation computers Parallel processing (Electronic computers) |
| volume_link | (DE-604)BV010943497 |
| work_keys_str_mv | AT nakashimahiroshi faultsimulationonparallelinferencemachines AT satohreiko faultsimulationonparallelinferencemachines |