Electromigration inside logic cells modeling, analyzing and mitigating signal electromigration in NanoCMOS von Posser, Gracieli, Sapatnekar, Sachin S., Reis, Ricardo

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Thermally-aware design von Zhan, Yong, Kumar, Sanjay V., Sapatnekar, Sachin S.

Design automation for timing driven layout synthesis von Sapatnekar, Sachin S., Kang, Sung-Mo S.

Design Automation for Timing-Driven Layout Synthesis von Sapatnekar, Sachin S., Kang, Sung-Mo

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Designing digital computer systems with Verilog von Lilja, David J., Sapatnekar, Sachin S.

Timing analysis and optimization of sequential circuits von Maheshwari, Naresh, Sapatnekar, Sachin S.

Timing Analysis and Optimization of Sequential Circuits von Maheshwari, Naresh, Sapatnekar, Sachin S.

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