Reconfigurable system design and verification:
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boca Raton [u.a.]
CRC Press
2009
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis Klappentext |
| Beschreibung: | 268 S. Ill., graph. Darst. |
| ISBN: | 9781420062663 |
Internformat
MARC
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| 100 | 1 | |a Hsiung, Pao-Ann |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Reconfigurable system design and verification |c Pao-Ann Hsiung ; Marco D. Santambrogio ; Chun-Hsian Huang |
| 264 | 1 | |a Boca Raton [u.a.] |b CRC Press |c 2009 | |
| 300 | |a 268 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Embedded computer systems | |
| 650 | 4 | |a System design | |
| 650 | 4 | |a Computer systems |x Verification | |
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| 689 | 0 | 3 | |a Verifikation |0 (DE-588)4135577-5 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Santambrogio, Marco D. |e Verfasser |4 aut | |
| 700 | 1 | |a Huang, Chun-Hsian |e Verfasser |4 aut | |
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| 999 | |a oai:aleph.bib-bvb.de:BVB01-017096124 | ||
Datensatz im Suchindex
| _version_ | 1804138587683291136 |
|---|---|
| adam_text | Contents
Preface
1
Introduction
to
Reconfigurable Computing
1
1.1
Why
Reconfigurable Computing?
................ 2
1.2
What is
Reconfigurable Computing?
.............. 3
1.3
From Codesign to Reconfiguration
............... 4
1.4
Reconfiguration Technology
................... 6
1.5
Reconfiguration Tools
and Platforms
.............. 7
1.6
Design
and Verification Methodologies .............
8
1.7
Application Examples
...................... 9
1.7.1
Embedded
Systems
.................... 10
1.7.2
Network
Security
Applications
............. 10
1.7.3
Multimedia Applications
................. 11
1.7.4
Scientific
Computing
................... 11
1.7.5
Reconfigurable
SAT Solvers...............
12
2
FPGA Technology
and Dynamic Reconfiguration
15
2.1
FPGA Overview
......................... 16
2.1.1
FPGA Architecture
................... 17
2.2
The Configuration
Bitstream
.................. 21
2.2.1
Overall
Bitstream
Structure
............... 22
2.2.2
Packet Headers
...................... 22
2.2.3
Configuration Registers
................. 23
2.2.4
Frame Indexing
...................... 25
2.3
FPGA Families and Models
................... 26
2.3.1
Spartan
3......................... 27
2.3.2
Virtex II Pro
....................... 27
2.3.3
Virtex
4.......................... 28
2.4
Configuration Conventions and File Formats
.......... 30
2.4.1
Configuration Resources Numbering Scheme
...... 30
2.4.2
The
RPM
Grid
...................... 31
2.4.3
UCF File Format
..................... 33
2.5
A Bird s-Eye View of
Reconfigurable
Systems
......... 33
2.6
Reconfiguration Characterization
................ 35
2.6.1
Complete vs. Partial Reconfiguration: An Overview
of Different Techniques
.................. 36
2.6.2
Reconfigurable
Architectures: The Five Ws
...... 38
2.7
Reconfigurable
Architecture Examples
............. 41
3
Reconfigurable Hardware Design
45
3.1
Model
............................... 46
3.2
Partitioning for
Reconfigurable
Architectures
......... 48
3.2.1
Temporal
Partitioning Approaches
........... 49
3.2.2
Spatial and Temporal Partitioning Approaches
.... 53
3.2.3
Regularity Extraction
.................. 54
3.2.4
Tree-Shaped Recurrent Structure Detection
...... 55
3.2.5
The DRESD Partitioning-Based Approach
....... 60
3.3
Scheduling Techniques
...................... 73
3.3.1
Related Work
....................... 73
3.3.2
ILP Formulation
..................... 75
3.3.3
Heuristic
.......................... 78
4
Operating System for
Reconfigurable
Systems
87
4.1
Motivation for OS4RS
...................... 87
4.2
Requirements for OS4RS
..................... 88
4.3
Layered Architecture for OS4RS
................ 90
4.3.1
Hardware Layer
...................... 91
4.3.2
Configuration Layer
................... 93
4.3.3
Placement Layer
..................... 93
4.3.4
Scheduling Layer
..................... 103
4.3.5
Module Layer
....................... 119
4.3.6
Application Layer
..................... 122
4.4
OS4RS Examples
......................... 123
5
Dynamic
Reconfigurable
Systems Design Flows
127
5.1
System Design Flows
....................... 127
5.1.1
Basic Flows
........................ 128
5.1.2
Generic Flows
....................... 129
5.2
Reconfigurable
System Design Flow: Structure and Implemen¬
tation
............................... 132
5.3
The Hardware Side of the Design Flow
............. 135
5.3.1
System Description Phase
................ 135
5.3.2
Design Synthesis and Placement Constraints Assign¬
ment Phase
........................ 142
5.3.3
System Generation Phase
................ 150
6
Reconfigurable
System Verification
155
6.1
System-Level Verification Techniques
.............. 155
6.1.1
Formal Verification
.................... 155
6.1.2
Language Approach
................... 156
6.2
Hardware-Software Coverification
................ 157
6.2.1
Hardware-Software Co-Simulation
........... 158
6.2.2
Hardware-Software Prototyping
............. 159
6.3
Reconfigurable
System Simulation Frameworks
........ 159
6.3.1
Overview of Frameworks
................. 161
6.4
Perfecto
Framework
....................... 162
6.4.1
Reconfigurable
Architecture Model
........... 163
6.4.2
Application Model
.................... 169
6.4.3
Partitioning
........................ 171
6.4.4
Scheduling
......................... 173
6.4.5
Placement
......................... 174
6.4.6
Performance Evaluation Results
............. 176
6.4.7
Application Examples
.................. 177
7
Dynamically Partially
Reconfigurable
System Design Imple¬
mentation
185
7.1
Partial Reconfiguration on Xilinx Virtex Family FPGAs
. . . 186
7.2
Early Access Partial Reconfiguration Design Flow
.......189
7.2.1
Design Partitioning and Synthesis
...........192
7.2.2
Design Budgeting
.....................195
7.2.3
Non-PR Design
......................196
7.2.4 Top-Level
Implementation
................197
7.2.5
Static Logic Implementation
...............197
7.2.6
PR Block Implementation
................198
7.2.7
Merge
...........................198
7.3
Creating Partially
Reconfigurable
Hardware Design
......199
7.4
Software-Controlled Partially
Reconfigurable
Design
.....207
7.5
Operating System for
Reconfigurable
Systems
.........217
References
225
Index
245
ing
RELONFIEURABLE SYSTEM
DE5IEN
AND VERIFICATION
Reconfigurable
systems have pervaded nearly all fields of computation and will
continue to do so for the foreseeable future.
Reconfigurable
System Design and
Verification provides a compendium of design and verification techniques for
reconfigurable
systems, allowing you to quickly search for a technique and
determine if it is appropriate to the task at hand. It bridges the gap between the
need for
reconfigurable
computing education and the burgeoning development
of numerous different techniques in the design and verification of
reconfigurable
systems in various application domains.
The text explains topics in such a way that they can be immediately grasped and
put into practice. It starts with an overview of
reconfigurable
computing
architectures and platforms and demonstrates how to develop
reconfigurable
systems. This sets up the discussion of the hardware, software, and system
techniques that form the core of the text. The authors classify design and verification
techniques into primary and secondary categories, allowing the appropriate ones
to be easily located and compared. The techniques discussed range from system
modeling and system-level design to co-simulation and formal verification. Case
studies illustrating real-world applications, detailed explanations of complex
algorithms, and self-explaining illustrations add depth to the presentation.
Comprehensively covering all techniques related to the hardware-software design
and verification of
reconfigurable
systems, this book provides a single source for
information that otherwise would have been dispersed among the literature,
making it very difficult to search, compare, and select the technique most suitable.
The authors do it all for you, making it easy to find the techniques that fit your
system requirements, without having to surf the net or digital libraries to find the
candidate techniques and compare them yourself.
|
| any_adam_object | 1 |
| author | Hsiung, Pao-Ann Santambrogio, Marco D. Huang, Chun-Hsian |
| author_facet | Hsiung, Pao-Ann Santambrogio, Marco D. Huang, Chun-Hsian |
| author_role | aut aut aut |
| author_sort | Hsiung, Pao-Ann |
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| callnumber-sort | TK 47895 E42 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 150 |
| ctrlnum | (OCoLC)154683836 (DE-599)BVBBV035291073 |
| dewey-full | 004.2/1 |
| dewey-hundreds | 000 - Computer science, information, general works |
| dewey-ones | 004 - Computer science |
| dewey-raw | 004.2/1 |
| dewey-search | 004.2/1 |
| dewey-sort | 14.2 11 |
| dewey-tens | 000 - Computer science, information, general works |
| discipline | Informatik |
| format | Book |
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| id | DE-604.BV035291073 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T21:30:34Z |
| institution | BVB |
| isbn | 9781420062663 |
| language | English |
| lccn | 2008044105 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017096124 |
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| physical | 268 S. Ill., graph. Darst. |
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| publisher | CRC Press |
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| spelling | Hsiung, Pao-Ann Verfasser aut Reconfigurable system design and verification Pao-Ann Hsiung ; Marco D. Santambrogio ; Chun-Hsian Huang Boca Raton [u.a.] CRC Press 2009 268 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Embedded computer systems System design Computer systems Verification Systementwurf (DE-588)4261480-6 gnd rswk-swf Computer (DE-588)4070083-5 gnd rswk-swf Verifikation (DE-588)4135577-5 gnd rswk-swf Rekonfiguration (DE-588)4306238-6 gnd rswk-swf Computer (DE-588)4070083-5 s Rekonfiguration (DE-588)4306238-6 s Systementwurf (DE-588)4261480-6 s Verifikation (DE-588)4135577-5 s DE-604 Santambrogio, Marco D. Verfasser aut Huang, Chun-Hsian Verfasser aut Digitalisierung UB Bayreuth application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017096124&sequence=000003&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis Digitalisierung UB Bayreuth application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017096124&sequence=000004&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA Klappentext |
| spellingShingle | Hsiung, Pao-Ann Santambrogio, Marco D. Huang, Chun-Hsian Reconfigurable system design and verification Embedded computer systems System design Computer systems Verification Systementwurf (DE-588)4261480-6 gnd Computer (DE-588)4070083-5 gnd Verifikation (DE-588)4135577-5 gnd Rekonfiguration (DE-588)4306238-6 gnd |
| subject_GND | (DE-588)4261480-6 (DE-588)4070083-5 (DE-588)4135577-5 (DE-588)4306238-6 |
| title | Reconfigurable system design and verification |
| title_auth | Reconfigurable system design and verification |
| title_exact_search | Reconfigurable system design and verification |
| title_full | Reconfigurable system design and verification Pao-Ann Hsiung ; Marco D. Santambrogio ; Chun-Hsian Huang |
| title_fullStr | Reconfigurable system design and verification Pao-Ann Hsiung ; Marco D. Santambrogio ; Chun-Hsian Huang |
| title_full_unstemmed | Reconfigurable system design and verification Pao-Ann Hsiung ; Marco D. Santambrogio ; Chun-Hsian Huang |
| title_short | Reconfigurable system design and verification |
| title_sort | reconfigurable system design and verification |
| topic | Embedded computer systems System design Computer systems Verification Systementwurf (DE-588)4261480-6 gnd Computer (DE-588)4070083-5 gnd Verifikation (DE-588)4135577-5 gnd Rekonfiguration (DE-588)4306238-6 gnd |
| topic_facet | Embedded computer systems System design Computer systems Verification Systementwurf Computer Verifikation Rekonfiguration |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017096124&sequence=000003&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017096124&sequence=000004&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA |
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