Data orchestration in deep learning accelerators:
Intro -- Preface -- Acknowledgments -- Introduction to Data Orchestration -- Deep Neural Networks (DNNs) -- DNN Training and Inference -- DNN Architectures and Layer Types -- Popular DNN Models -- DNN Accelerators -- Computations within DNNs -- Challenge: Data Movement -- Opportunity: Data Reuse --...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
[San Rafael]
Morgan & Claypool Publishers
[2020]
|
| Schriftenreihe: | Synthesis lectures on computer architecture
#52 |
| Schlagworte: | |
| Online-Zugang: | TUM01 |
| Zusammenfassung: | Intro -- Preface -- Acknowledgments -- Introduction to Data Orchestration -- Deep Neural Networks (DNNs) -- DNN Training and Inference -- DNN Architectures and Layer Types -- Popular DNN Models -- DNN Accelerators -- Computations within DNNs -- Challenge: Data Movement -- Opportunity: Data Reuse -- Book Overview -- Dataflow and Data Reuse -- Data Reuse Opportunities -- Data Reuse in 1D Convolution -- Dataflows and Mappings -- Deep Dive into Dataflows and Mappings -- Harnessing Data Reuse via Hardware Support -- Dataflows and Data Reuse in CONV2D -- CONV2D Operation -- Data Dimension Coupling and Data Reuse Opportunities -- Data Reuse in a CONV2D Example -- Convolution as Matrix Multiplication -- Summary -- Buffer Hierarchies -- Motivation -- Classifying Buffering Approaches -- Implicit vs. Explicit Orchestration -- Coupled vs. Decoupled Orchestration -- Synchronization Concerns -- The Buffet Storage Idiom -- Buffet Operational Behavior -- Buffet Synchronization Details -- Example Orchestration with Buffets -- Automatically Deriving Configuration -- Composition of Buffer Idioms -- Buffer Hierarchies -- Sharing Fills via Multicast -- Sharing Physical RAMs Efficiently -- Example of Hierarchical Orchestration -- Other Relevant Buffering Idioms for Accelerators -- Research Needs for Accelerator Buffer Hierarchies -- Summary -- Networks-on-Chip -- Communication Phases -- Traditional Networks-on-Chip -- Topology -- Routing -- Flow Control -- Router Microarchitecture -- Challenges with Traditional NoCs -- Specialized NoCs for DNN Accelerators -- Topology -- Routing -- Flow Control -- Leveraging Reuse via the NoC -- Implications of Temporal Reuse -- Implications of Spatial Reuse -- Tying it Together: From Dataflow to Traffic Flow -- Summary -- Putting it Together: Architecting a DNN Accelerator -- Design Flow -- Target Specs and Constraints |
| Beschreibung: | Description based on publisher supplied metadata and other sources |
| Beschreibung: | 1 Online-Ressource |
| ISBN: | 9781681738703 |
Internformat
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Datensatz im Suchindex
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| id | DE-604.BV047030890 |
| illustrated | Not Illustrated |
| index_date | 2024-07-03T16:02:14Z |
| indexdate | 2024-07-10T09:00:38Z |
| institution | BVB |
| isbn | 9781681738703 |
| language | English |
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| publishDate | 2020 |
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| record_format | marc |
| series | Synthesis lectures on computer architecture |
| series2 | Synthesis lectures on computer architecture |
| spelling | Krishna, Tushar Verfasser (DE-588)1206961228 aut Data orchestration in deep learning accelerators Tushar Krishna (Georgia Institute of Technology), Hyoukjun Kwon (Georgia Institute of Technology), Angshuman Parashar (NVIDIA), Michael Pellauer (NVIDIA), Ananda Samajdar (Georgia Institute of Technology) [San Rafael] Morgan & Claypool Publishers [2020] 1 Online-Ressource txt rdacontent c rdamedia cr rdacarrier Synthesis lectures on computer architecture #52 Description based on publisher supplied metadata and other sources Intro -- Preface -- Acknowledgments -- Introduction to Data Orchestration -- Deep Neural Networks (DNNs) -- DNN Training and Inference -- DNN Architectures and Layer Types -- Popular DNN Models -- DNN Accelerators -- Computations within DNNs -- Challenge: Data Movement -- Opportunity: Data Reuse -- Book Overview -- Dataflow and Data Reuse -- Data Reuse Opportunities -- Data Reuse in 1D Convolution -- Dataflows and Mappings -- Deep Dive into Dataflows and Mappings -- Harnessing Data Reuse via Hardware Support -- Dataflows and Data Reuse in CONV2D -- CONV2D Operation -- Data Dimension Coupling and Data Reuse Opportunities -- Data Reuse in a CONV2D Example -- Convolution as Matrix Multiplication -- Summary -- Buffer Hierarchies -- Motivation -- Classifying Buffering Approaches -- Implicit vs. Explicit Orchestration -- Coupled vs. Decoupled Orchestration -- Synchronization Concerns -- The Buffet Storage Idiom -- Buffet Operational Behavior -- Buffet Synchronization Details -- Example Orchestration with Buffets -- Automatically Deriving Configuration -- Composition of Buffer Idioms -- Buffer Hierarchies -- Sharing Fills via Multicast -- Sharing Physical RAMs Efficiently -- Example of Hierarchical Orchestration -- Other Relevant Buffering Idioms for Accelerators -- Research Needs for Accelerator Buffer Hierarchies -- Summary -- Networks-on-Chip -- Communication Phases -- Traditional Networks-on-Chip -- Topology -- Routing -- Flow Control -- Router Microarchitecture -- Challenges with Traditional NoCs -- Specialized NoCs for DNN Accelerators -- Topology -- Routing -- Flow Control -- Leveraging Reuse via the NoC -- Implications of Temporal Reuse -- Implications of Spatial Reuse -- Tying it Together: From Dataflow to Traffic Flow -- Summary -- Putting it Together: Architecting a DNN Accelerator -- Design Flow -- Target Specs and Constraints Electronic books Kwon, Hyoukjun Verfasser aut Parashar, Angshuman Verfasser aut Pellauer, Michael Verfasser aut Samajdar, Ananda Verfasser aut Erscheint auch als Druck-Ausgabe, Hardcover 978-1-68173-871-0 Erscheint auch als Druck-Ausgabe, Paperback 978-1-68173-869-7 Synthesis lectures on computer architecture #52 (DE-604)BV047042546 52 |
| spellingShingle | Krishna, Tushar Kwon, Hyoukjun Parashar, Angshuman Pellauer, Michael Samajdar, Ananda Data orchestration in deep learning accelerators Synthesis lectures on computer architecture |
| title | Data orchestration in deep learning accelerators |
| title_auth | Data orchestration in deep learning accelerators |
| title_exact_search | Data orchestration in deep learning accelerators |
| title_exact_search_txtP | Data orchestration in deep learning accelerators |
| title_full | Data orchestration in deep learning accelerators Tushar Krishna (Georgia Institute of Technology), Hyoukjun Kwon (Georgia Institute of Technology), Angshuman Parashar (NVIDIA), Michael Pellauer (NVIDIA), Ananda Samajdar (Georgia Institute of Technology) |
| title_fullStr | Data orchestration in deep learning accelerators Tushar Krishna (Georgia Institute of Technology), Hyoukjun Kwon (Georgia Institute of Technology), Angshuman Parashar (NVIDIA), Michael Pellauer (NVIDIA), Ananda Samajdar (Georgia Institute of Technology) |
| title_full_unstemmed | Data orchestration in deep learning accelerators Tushar Krishna (Georgia Institute of Technology), Hyoukjun Kwon (Georgia Institute of Technology), Angshuman Parashar (NVIDIA), Michael Pellauer (NVIDIA), Ananda Samajdar (Georgia Institute of Technology) |
| title_short | Data orchestration in deep learning accelerators |
| title_sort | data orchestration in deep learning accelerators |
| volume_link | (DE-604)BV047042546 |
| work_keys_str_mv | AT krishnatushar dataorchestrationindeeplearningaccelerators AT kwonhyoukjun dataorchestrationindeeplearningaccelerators AT parasharangshuman dataorchestrationindeeplearningaccelerators AT pellauermichael dataorchestrationindeeplearningaccelerators AT samajdarananda dataorchestrationindeeplearningaccelerators |