A designer's guide to asynchronous VLSI:
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| Main Authors: | , , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Cambridge [u.a.]
Cambridge University Press
2010
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| Subjects: | |
| Online Access: | Cover image Inhaltsverzeichnis |
| Physical Description: | XII, 339 S. graph. Darst. |
| ISBN: | 9780521872447 |
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Record in the Search Index
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| adam_text | A DESIGNER S GUIDE TO VLSI
/ BEEREL, PETER A.
: 2010
TABLE OF CONTENTS / INHALTSVERZEICHNIS
1. INTRODUCTION; 2. CHANNEL-BASED ASYNCHRONOUS DESIGN; 3. MODELING
CHANNEL-BASED DESIGNS; 4. PIPELINE PERFORMANCE; 5. PERFORMANCE ANALYSIS
AND OPTIMIZATION; 6. DEADLOCK; 7. A TAXONOMY OF DESIGN STYLES; 8.
SYNTHESIS-BASED CONTROLLER DESIGN; 9. MICROPIPELINE DESIGN; 10.
SYNTAX-DIRECTED TRANSLATION; 11. QDI PIPELINE TEMPLATES; 12. TIMED
PIPELINE TEMPLATES; 13. SINGLE-TRACK PIPELINE TEMPLATES; 14.
ASYNCHRONOUS CROSSBAR.
DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT.
|
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| isbn | 9780521872447 |
| language | English |
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| spelling | Beerel, Peter A. Verfasser aut A designer's guide to asynchronous VLSI Peter A. Beerel ; Recep O. Ozdag ; Marcos Ferretti Cambridge [u.a.] Cambridge University Press 2010 XII, 339 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Integrated circuits Very large scale integration Computer-aided design Integrated circuits Very large scale integration Design and construction Ozdag, Recep O. Verfasser aut Ferretti, Marcos Verfasser aut http://assets.cambridge.org/97805218/72447/cover/9780521872447.jpg Cover image LoC Fremddatenuebernahme application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=019011504&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Beerel, Peter A. Ozdag, Recep O. Ferretti, Marcos A designer's guide to asynchronous VLSI Integrated circuits Very large scale integration Computer-aided design Integrated circuits Very large scale integration Design and construction |
| title | A designer's guide to asynchronous VLSI |
| title_auth | A designer's guide to asynchronous VLSI |
| title_exact_search | A designer's guide to asynchronous VLSI |
| title_full | A designer's guide to asynchronous VLSI Peter A. Beerel ; Recep O. Ozdag ; Marcos Ferretti |
| title_fullStr | A designer's guide to asynchronous VLSI Peter A. Beerel ; Recep O. Ozdag ; Marcos Ferretti |
| title_full_unstemmed | A designer's guide to asynchronous VLSI Peter A. Beerel ; Recep O. Ozdag ; Marcos Ferretti |
| title_short | A designer's guide to asynchronous VLSI |
| title_sort | a designer s guide to asynchronous vlsi |
| topic | Integrated circuits Very large scale integration Computer-aided design Integrated circuits Very large scale integration Design and construction |
| topic_facet | Integrated circuits Very large scale integration Computer-aided design Integrated circuits Very large scale integration Design and construction |
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