Verfügbarkeit: Network processor design :

Network processor design :: issues and practices. Volume 1 /

As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from ta...

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Weitere Verfasser:	Crowley, Patrick, 1974-, Hadimioglu, Haldun, Onufryk, Peter Z.
Format:	Elektronisch E-Book
Sprache:	English
Veröffentlicht:	Burlington : Elsevier, 2002.
Schriftenreihe:	Morgan Kaufmann Series in Computer Architecture and Design.
Schlagworte:	Microprocessors. Application-specific integrated circuits. Computer networks > Equipment and supplies. Circuits intégrés à la demande. COMPUTERS > Logic Design. TECHNOLOGY & ENGINEERING > Electronics > Circuits > Logic. TECHNOLOGY & ENGINEERING > Electronics > Circuits > VLSI & ULSI. Application-specific integrated circuits Computer networks > Equipment and supplies Microprocessors
Online-Zugang:	Volltext
Zusammenfassung:	As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors. Programmable yet application-specific, their designs are tailored to efficiently implement communications applications such as routing, protocol analysis, voice and dat.
Beschreibung:	1 online resource (353 pages)
ISBN:	9780080512495 0080512496

Internformat

MARC


LEADER	00000cam a2200000Mi 4500
001	ZDB-4-EBA-ocn719319895
003	OCoLC
005	20241004212047.0
006	m o d
007	cr \|n\|---\|\|\|\|\|
008	110502s2002 vtu o 000 0 eng d
040			\|a EBLCP \|b eng \|e pn \|c EBLCP \|d OCLCQ \|d N$T \|d OCLCQ \|d OCLCO \|d OCLCQ \|d OCLCF \|d OCLCQ \|d YDXCP \|d OCLCQ \|d MERUC \|d OCLCQ \|d VTS \|d OCLCQ \|d AJS \|d OCLCO \|d OCLCQ \|d OCLCO \|d OCLCL \|d OCLCQ
019			\|a 808684017
020			\|a 9780080512495 \|q (electronic bk.)
020			\|a 0080512496 \|q (electronic bk.)
035			\|a (OCoLC)719319895 \|z (OCoLC)808684017
050		4	\|a TK7895.M5
072		7	\|a COM \|x 036000 \|2 bisacsh
072		7	\|a TEC \|x 008030 \|2 bisacsh
072		7	\|a TEC \|x 008050 \|2 bisacsh
082	7		\|a 621.395 \|2 23
049			\|a MAIN
245	0	0	\|a Network processor design : \|b issues and practices. \|n Volume 1 / \|c edited by Patrick Crowley [and others].
260			\|a Burlington : \|b Elsevier, \|c 2002.
300			\|a 1 online resource (353 pages)
336			\|a text \|b txt \|2 rdacontent
337			\|a computer \|b c \|2 rdamedia
338			\|a online resource \|b cr \|2 rdacarrier
490	1		\|a The Morgan Kaufmann Series in Computer Architecture and Design ; \|v v. 1
505	0		\|a Front Cover; Front Cover; Network Processor Design Issues and Practices; Network Processor Design Issues and Practices; Copyright Page; Copyright Page; Contents; Contents; Preface; Preface; Chapter 1. Network Processors: An Introduction to Design Issues; Chapter 1. Network Processors: An Introduction to Design Issues; 1.1 Design Challenges; 1.1 Design Challenges; 1.2 Design Techniques; 1.2 Design Techniques; 1.3 Challenges and Conclusions; 1.3 Challenges and Conclusions; PART I: DESIGN PRINCIPLES; PART I: DESIGN PRINCIPLES; Chapter 2. Benchmarking Network Processors.
505	8		\|a Chapter 2. Benchmarking Network ProcessorsChapter 3. A Methodology and Simulator for the Study of Network Processors; Chapter 3. A Methodology and Simulator for the Study of Network Processors; Chapter 4. Design Space Exploration of Network Processor Architectures; Chapter 4. Design Space Exploration of Network Processor Architectures; Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing; Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing.
505	8		\|a Chapter 6. A Network Processor Performance and Design Model with Benchmark ParameterizationChapter 6. A Network Processor Performance and Design Model with Benchmark Parameterization; Chapter 7. A Benchmarking Methodology for Network Processors; Chapter 7. A Benchmarking Methodology for Network Processors; Chapter 8. A Modeling Framework for Network Processor Systems; Chapter 8. A Modeling Framework for Network Processor Systems; PART II: PRACTICES; PART II: PRACTICES; Chapter 9. An Industry Analyst's Perspective on Networ k Processors.
505	8		\|a Chapter 9. An Industry Analyst's Perspective on Networ k ProcessorsChapter 10. Agere Systems--Communications Optimized PayloadPlus Network Processor Architecture; Chapter 10. Agere Systems--Communications Optimized PayloadPlus Network Processor Architecture; Chapter 11. Cisco Systems-- Toaster 2; Chapter 11. Cisco Systems-- Toaster 2; Chapter 12. IBM--PowerNP Network Processor; Chapter 12. IBM--PowerNP Network Processor; Chapter 13. Intel Corporation--Intel IXP2400 Network Processor: A Second-Generation Intel NPU.
505	8		\|a Chapter 13. Intel Corporation--Intel IXP2400 Network Processor: A Second-Generation Intel NPUChapter 14. Motorola--C-5e Network Processor; Chapter 14. Motorola--C-5e Network Processor; Chapter 15. PMC-Sierra, Inc.-- ClassiPI; Chapter 15. PMC-Sierra, Inc.-- ClassiPI; Chapter 16. TranSwitch--ASPEN: Flexible Network Processing for Access Solutions; Chapter 16. TranSwitch--ASPEN: Flexible Network Processing for Access Solutions; Index; Index; About the Editors; About the Editors.
520			\|a As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors. Programmable yet application-specific, their designs are tailored to efficiently implement communications applications such as routing, protocol analysis, voice and dat.
588	0		\|a Print version record.
650		0	\|a Microprocessors. \|0 http://id.loc.gov/authorities/subjects/sh85084898
650		0	\|a Application-specific integrated circuits. \|0 http://id.loc.gov/authorities/subjects/sh89004045
650		0	\|a Computer networks \|x Equipment and supplies.
650		6	\|a Circuits intégrés à la demande.
650		7	\|a COMPUTERS \|x Logic Design. \|2 bisacsh
650		7	\|a TECHNOLOGY & ENGINEERING \|x Electronics \|x Circuits \|x Logic. \|2 bisacsh
650		7	\|a TECHNOLOGY & ENGINEERING \|x Electronics \|x Circuits \|x VLSI & ULSI. \|2 bisacsh
650		7	\|a Application-specific integrated circuits \|2 fast
650		7	\|a Computer networks \|x Equipment and supplies \|2 fast
650		7	\|a Microprocessors \|2 fast
700	1		\|a Crowley, Patrick, \|d 1974- \|1 https://id.oclc.org/worldcat/entity/E39PCjxRrTYqDqdYmvPwkWtcpq \|0 http://id.loc.gov/authorities/names/nb2003068155
700	1		\|a Hadimioglu, Haldun.
700	1		\|a Onufryk, Peter Z.
776	0	8	\|i Print version: \|a Franklin, Mark A. \|t Network Processor Design : Issues and Practices, Volume 1. \|d Burlington : Elsevier, ©2002 \|z 9781558608757
830		0	\|a Morgan Kaufmann Series in Computer Architecture and Design.
856	4	0	\|l FWS01 \|p ZDB-4-EBA \|q FWS_PDA_EBA \|u https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=241119 \|3 Volltext
938			\|a EBL - Ebook Library \|b EBLB \|n EBL349541
938			\|a EBSCOhost \|b EBSC \|n 241119
938			\|a YBP Library Services \|b YANK \|n 2907466
994			\|a 92 \|b GEBAY
912			\|a ZDB-4-EBA
049			\|a DE-863

Datensatz im Suchindex

DE-BY-FWS_katkey	ZDB-4-EBA-ocn719319895
_version_	1816881758039179265
adam_text
any_adam_object
author2	Crowley, Patrick, 1974- Hadimioglu, Haldun Onufryk, Peter Z.
author2_role
author2_variant	p c pc h h hh p z o pz pzo
author_GND	http://id.loc.gov/authorities/names/nb2003068155
author_facet	Crowley, Patrick, 1974- Hadimioglu, Haldun Onufryk, Peter Z.
author_sort	Crowley, Patrick, 1974-
building	Verbundindex
bvnumber	localFWS
callnumber-first	T - Technology
callnumber-label	TK7895
callnumber-raw	TK7895.M5
callnumber-search	TK7895.M5
callnumber-sort	TK 47895 M5
callnumber-subject	TK - Electrical and Nuclear Engineering
collection	ZDB-4-EBA
contents	Front Cover; Front Cover; Network Processor Design Issues and Practices; Network Processor Design Issues and Practices; Copyright Page; Copyright Page; Contents; Contents; Preface; Preface; Chapter 1. Network Processors: An Introduction to Design Issues; Chapter 1. Network Processors: An Introduction to Design Issues; 1.1 Design Challenges; 1.1 Design Challenges; 1.2 Design Techniques; 1.2 Design Techniques; 1.3 Challenges and Conclusions; 1.3 Challenges and Conclusions; PART I: DESIGN PRINCIPLES; PART I: DESIGN PRINCIPLES; Chapter 2. Benchmarking Network Processors. Chapter 2. Benchmarking Network ProcessorsChapter 3. A Methodology and Simulator for the Study of Network Processors; Chapter 3. A Methodology and Simulator for the Study of Network Processors; Chapter 4. Design Space Exploration of Network Processor Architectures; Chapter 4. Design Space Exploration of Network Processor Architectures; Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing; Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing. Chapter 6. A Network Processor Performance and Design Model with Benchmark ParameterizationChapter 6. A Network Processor Performance and Design Model with Benchmark Parameterization; Chapter 7. A Benchmarking Methodology for Network Processors; Chapter 7. A Benchmarking Methodology for Network Processors; Chapter 8. A Modeling Framework for Network Processor Systems; Chapter 8. A Modeling Framework for Network Processor Systems; PART II: PRACTICES; PART II: PRACTICES; Chapter 9. An Industry Analyst's Perspective on Networ k Processors. Chapter 9. An Industry Analyst's Perspective on Networ k ProcessorsChapter 10. Agere Systems--Communications Optimized PayloadPlus Network Processor Architecture; Chapter 10. Agere Systems--Communications Optimized PayloadPlus Network Processor Architecture; Chapter 11. Cisco Systems-- Toaster 2; Chapter 11. Cisco Systems-- Toaster 2; Chapter 12. IBM--PowerNP Network Processor; Chapter 12. IBM--PowerNP Network Processor; Chapter 13. Intel Corporation--Intel IXP2400 Network Processor: A Second-Generation Intel NPU. Chapter 13. Intel Corporation--Intel IXP2400 Network Processor: A Second-Generation Intel NPUChapter 14. Motorola--C-5e Network Processor; Chapter 14. Motorola--C-5e Network Processor; Chapter 15. PMC-Sierra, Inc.-- ClassiPI; Chapter 15. PMC-Sierra, Inc.-- ClassiPI; Chapter 16. TranSwitch--ASPEN: Flexible Network Processing for Access Solutions; Chapter 16. TranSwitch--ASPEN: Flexible Network Processing for Access Solutions; Index; Index; About the Editors; About the Editors.
ctrlnum	(OCoLC)719319895
dewey-full	621.395
dewey-hundreds	600 - Technology (Applied sciences)
dewey-ones	621 - Applied physics
dewey-raw	621.395
dewey-search	621.395
dewey-sort	3621.395
dewey-tens	620 - Engineering and allied operations
discipline	Elektrotechnik / Elektronik / Nachrichtentechnik
format	Electronic eBook
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>05946cam a2200637Mi 4500</leader><controlfield tag="001">ZDB-4-EBA-ocn719319895</controlfield><controlfield tag="003">OCoLC</controlfield><controlfield tag="005">20241004212047.0</controlfield><controlfield tag="006">m o d </controlfield><controlfield tag="007">cr \|n\|---\|\|\|\|\|</controlfield><controlfield tag="008">110502s2002 vtu o 000 0 eng d</controlfield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">EBLCP</subfield><subfield code="b">eng</subfield><subfield code="e">pn</subfield><subfield code="c">EBLCP</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">N$T</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">OCLCO</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">OCLCF</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">YDXCP</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">MERUC</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">VTS</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">AJS</subfield><subfield code="d">OCLCO</subfield><subfield code="d">OCLCQ</subfield><subfield code="d">OCLCO</subfield><subfield code="d">OCLCL</subfield><subfield code="d">OCLCQ</subfield></datafield><datafield tag="019" ind1=" " ind2=" "><subfield code="a">808684017</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780080512495</subfield><subfield code="q">(electronic bk.)</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0080512496</subfield><subfield code="q">(electronic bk.)</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)719319895</subfield><subfield code="z">(OCoLC)808684017</subfield></datafield><datafield tag="050" ind1=" " ind2="4"><subfield code="a">TK7895.M5</subfield></datafield><datafield tag="072" ind1=" " ind2="7"><subfield code="a">COM</subfield><subfield code="x">036000</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="072" ind1=" " ind2="7"><subfield code="a">TEC</subfield><subfield code="x">008030</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="072" ind1=" " ind2="7"><subfield code="a">TEC</subfield><subfield code="x">008050</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="082" ind1="7" ind2=" "><subfield code="a">621.395</subfield><subfield code="2">23</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">MAIN</subfield></datafield><datafield tag="245" ind1="0" ind2="0"><subfield code="a">Network processor design :</subfield><subfield code="b">issues and practices.</subfield><subfield code="n">Volume 1 /</subfield><subfield code="c">edited by Patrick Crowley [and others].</subfield></datafield><datafield tag="260" ind1=" " ind2=" "><subfield code="a">Burlington :</subfield><subfield code="b">Elsevier,</subfield><subfield code="c">2002.</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource (353 pages)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">computer</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">online resource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">The Morgan Kaufmann Series in Computer Architecture and Design ;</subfield><subfield code="v">v. 1</subfield></datafield><datafield tag="505" ind1="0" ind2=" "><subfield code="a">Front Cover; Front Cover; Network Processor Design Issues and Practices; Network Processor Design Issues and Practices; Copyright Page; Copyright Page; Contents; Contents; Preface; Preface; Chapter 1. Network Processors: An Introduction to Design Issues; Chapter 1. Network Processors: An Introduction to Design Issues; 1.1 Design Challenges; 1.1 Design Challenges; 1.2 Design Techniques; 1.2 Design Techniques; 1.3 Challenges and Conclusions; 1.3 Challenges and Conclusions; PART I: DESIGN PRINCIPLES; PART I: DESIGN PRINCIPLES; Chapter 2. Benchmarking Network Processors.</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">Chapter 2. Benchmarking Network ProcessorsChapter 3. A Methodology and Simulator for the Study of Network Processors; Chapter 3. A Methodology and Simulator for the Study of Network Processors; Chapter 4. Design Space Exploration of Network Processor Architectures; Chapter 4. Design Space Exploration of Network Processor Architectures; Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing; Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing.</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">Chapter 6. A Network Processor Performance and Design Model with Benchmark ParameterizationChapter 6. A Network Processor Performance and Design Model with Benchmark Parameterization; Chapter 7. A Benchmarking Methodology for Network Processors; Chapter 7. A Benchmarking Methodology for Network Processors; Chapter 8. A Modeling Framework for Network Processor Systems; Chapter 8. A Modeling Framework for Network Processor Systems; PART II: PRACTICES; PART II: PRACTICES; Chapter 9. An Industry Analyst's Perspective on Networ k Processors.</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">Chapter 9. An Industry Analyst's Perspective on Networ k ProcessorsChapter 10. Agere Systems--Communications Optimized PayloadPlus Network Processor Architecture; Chapter 10. Agere Systems--Communications Optimized PayloadPlus Network Processor Architecture; Chapter 11. Cisco Systems-- Toaster 2; Chapter 11. Cisco Systems-- Toaster 2; Chapter 12. IBM--PowerNP Network Processor; Chapter 12. IBM--PowerNP Network Processor; Chapter 13. Intel Corporation--Intel IXP2400 Network Processor: A Second-Generation Intel NPU.</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">Chapter 13. Intel Corporation--Intel IXP2400 Network Processor: A Second-Generation Intel NPUChapter 14. Motorola--C-5e Network Processor; Chapter 14. Motorola--C-5e Network Processor; Chapter 15. PMC-Sierra, Inc.-- ClassiPI; Chapter 15. PMC-Sierra, Inc.-- ClassiPI; Chapter 16. TranSwitch--ASPEN: Flexible Network Processing for Access Solutions; Chapter 16. TranSwitch--ASPEN: Flexible Network Processing for Access Solutions; Index; Index; About the Editors; About the Editors.</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors. Programmable yet application-specific, their designs are tailored to efficiently implement communications applications such as routing, protocol analysis, voice and dat.</subfield></datafield><datafield tag="588" ind1="0" ind2=" "><subfield code="a">Print version record.</subfield></datafield><datafield tag="650" ind1=" " ind2="0"><subfield code="a">Microprocessors.</subfield><subfield code="0">http://id.loc.gov/authorities/subjects/sh85084898</subfield></datafield><datafield tag="650" ind1=" " ind2="0"><subfield code="a">Application-specific integrated circuits.</subfield><subfield code="0">http://id.loc.gov/authorities/subjects/sh89004045</subfield></datafield><datafield tag="650" ind1=" " ind2="0"><subfield code="a">Computer networks</subfield><subfield code="x">Equipment and supplies.</subfield></datafield><datafield tag="650" ind1=" " ind2="6"><subfield code="a">Circuits intégrés à la demande.</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">COMPUTERS</subfield><subfield code="x">Logic Design.</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING</subfield><subfield code="x">Electronics</subfield><subfield code="x">Circuits</subfield><subfield code="x">Logic.</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING</subfield><subfield code="x">Electronics</subfield><subfield code="x">Circuits</subfield><subfield code="x">VLSI & ULSI.</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Application-specific integrated circuits</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Computer networks</subfield><subfield code="x">Equipment and supplies</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Microprocessors</subfield><subfield code="2">fast</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Crowley, Patrick,</subfield><subfield code="d">1974-</subfield><subfield code="1">https://id.oclc.org/worldcat/entity/E39PCjxRrTYqDqdYmvPwkWtcpq</subfield><subfield code="0">http://id.loc.gov/authorities/names/nb2003068155</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Hadimioglu, Haldun.</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Onufryk, Peter Z.</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Print version:</subfield><subfield code="a">Franklin, Mark A.</subfield><subfield code="t">Network Processor Design : Issues and Practices, Volume 1.</subfield><subfield code="d">Burlington : Elsevier, ©2002</subfield><subfield code="z">9781558608757</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Morgan Kaufmann Series in Computer Architecture and Design.</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="l">FWS01</subfield><subfield code="p">ZDB-4-EBA</subfield><subfield code="q">FWS_PDA_EBA</subfield><subfield code="u">https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=241119</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="938" ind1=" " ind2=" "><subfield code="a">EBL - Ebook Library</subfield><subfield code="b">EBLB</subfield><subfield code="n">EBL349541</subfield></datafield><datafield tag="938" ind1=" " ind2=" "><subfield code="a">EBSCOhost</subfield><subfield code="b">EBSC</subfield><subfield code="n">241119</subfield></datafield><datafield tag="938" ind1=" " ind2=" "><subfield code="a">YBP Library Services</subfield><subfield code="b">YANK</subfield><subfield code="n">2907466</subfield></datafield><datafield tag="994" ind1=" " ind2=" "><subfield code="a">92</subfield><subfield code="b">GEBAY</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-4-EBA</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-863</subfield></datafield></record></collection>
id	ZDB-4-EBA-ocn719319895
illustrated	Not Illustrated
indexdate	2024-11-27T13:17:48Z
institution	BVB
isbn	9780080512495 0080512496
language	English
oclc_num	719319895
open_access_boolean
owner	MAIN DE-863 DE-BY-FWS
owner_facet	MAIN DE-863 DE-BY-FWS
physical	1 online resource (353 pages)
psigel	ZDB-4-EBA
publishDate	2002
publishDateSearch	2002
publishDateSort	2002
publisher	Elsevier,
record_format	marc
series	Morgan Kaufmann Series in Computer Architecture and Design.
series2	The Morgan Kaufmann Series in Computer Architecture and Design ;
spelling	Network processor design : issues and practices. Volume 1 / edited by Patrick Crowley [and others]. Burlington : Elsevier, 2002. 1 online resource (353 pages) text txt rdacontent computer c rdamedia online resource cr rdacarrier The Morgan Kaufmann Series in Computer Architecture and Design ; v. 1 Front Cover; Front Cover; Network Processor Design Issues and Practices; Network Processor Design Issues and Practices; Copyright Page; Copyright Page; Contents; Contents; Preface; Preface; Chapter 1. Network Processors: An Introduction to Design Issues; Chapter 1. Network Processors: An Introduction to Design Issues; 1.1 Design Challenges; 1.1 Design Challenges; 1.2 Design Techniques; 1.2 Design Techniques; 1.3 Challenges and Conclusions; 1.3 Challenges and Conclusions; PART I: DESIGN PRINCIPLES; PART I: DESIGN PRINCIPLES; Chapter 2. Benchmarking Network Processors. Chapter 2. Benchmarking Network ProcessorsChapter 3. A Methodology and Simulator for the Study of Network Processors; Chapter 3. A Methodology and Simulator for the Study of Network Processors; Chapter 4. Design Space Exploration of Network Processor Architectures; Chapter 4. Design Space Exploration of Network Processor Architectures; Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing; Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing. Chapter 6. A Network Processor Performance and Design Model with Benchmark ParameterizationChapter 6. A Network Processor Performance and Design Model with Benchmark Parameterization; Chapter 7. A Benchmarking Methodology for Network Processors; Chapter 7. A Benchmarking Methodology for Network Processors; Chapter 8. A Modeling Framework for Network Processor Systems; Chapter 8. A Modeling Framework for Network Processor Systems; PART II: PRACTICES; PART II: PRACTICES; Chapter 9. An Industry Analyst's Perspective on Networ k Processors. Chapter 9. An Industry Analyst's Perspective on Networ k ProcessorsChapter 10. Agere Systems--Communications Optimized PayloadPlus Network Processor Architecture; Chapter 10. Agere Systems--Communications Optimized PayloadPlus Network Processor Architecture; Chapter 11. Cisco Systems-- Toaster 2; Chapter 11. Cisco Systems-- Toaster 2; Chapter 12. IBM--PowerNP Network Processor; Chapter 12. IBM--PowerNP Network Processor; Chapter 13. Intel Corporation--Intel IXP2400 Network Processor: A Second-Generation Intel NPU. Chapter 13. Intel Corporation--Intel IXP2400 Network Processor: A Second-Generation Intel NPUChapter 14. Motorola--C-5e Network Processor; Chapter 14. Motorola--C-5e Network Processor; Chapter 15. PMC-Sierra, Inc.-- ClassiPI; Chapter 15. PMC-Sierra, Inc.-- ClassiPI; Chapter 16. TranSwitch--ASPEN: Flexible Network Processing for Access Solutions; Chapter 16. TranSwitch--ASPEN: Flexible Network Processing for Access Solutions; Index; Index; About the Editors; About the Editors. As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors. Programmable yet application-specific, their designs are tailored to efficiently implement communications applications such as routing, protocol analysis, voice and dat. Print version record. Microprocessors. http://id.loc.gov/authorities/subjects/sh85084898 Application-specific integrated circuits. http://id.loc.gov/authorities/subjects/sh89004045 Computer networks Equipment and supplies. Circuits intégrés à la demande. COMPUTERS Logic Design. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh Application-specific integrated circuits fast Computer networks Equipment and supplies fast Microprocessors fast Crowley, Patrick, 1974- https://id.oclc.org/worldcat/entity/E39PCjxRrTYqDqdYmvPwkWtcpq http://id.loc.gov/authorities/names/nb2003068155 Hadimioglu, Haldun. Onufryk, Peter Z. Print version: Franklin, Mark A. Network Processor Design : Issues and Practices, Volume 1. Burlington : Elsevier, ©2002 9781558608757 Morgan Kaufmann Series in Computer Architecture and Design. FWS01 ZDB-4-EBA FWS_PDA_EBA https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=241119 Volltext
spellingShingle	Network processor design : issues and practices. Morgan Kaufmann Series in Computer Architecture and Design. Front Cover; Front Cover; Network Processor Design Issues and Practices; Network Processor Design Issues and Practices; Copyright Page; Copyright Page; Contents; Contents; Preface; Preface; Chapter 1. Network Processors: An Introduction to Design Issues; Chapter 1. Network Processors: An Introduction to Design Issues; 1.1 Design Challenges; 1.1 Design Challenges; 1.2 Design Techniques; 1.2 Design Techniques; 1.3 Challenges and Conclusions; 1.3 Challenges and Conclusions; PART I: DESIGN PRINCIPLES; PART I: DESIGN PRINCIPLES; Chapter 2. Benchmarking Network Processors. Chapter 2. Benchmarking Network ProcessorsChapter 3. A Methodology and Simulator for the Study of Network Processors; Chapter 3. A Methodology and Simulator for the Study of Network Processors; Chapter 4. Design Space Exploration of Network Processor Architectures; Chapter 4. Design Space Exploration of Network Processor Architectures; Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing; Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing. Chapter 6. A Network Processor Performance and Design Model with Benchmark ParameterizationChapter 6. A Network Processor Performance and Design Model with Benchmark Parameterization; Chapter 7. A Benchmarking Methodology for Network Processors; Chapter 7. A Benchmarking Methodology for Network Processors; Chapter 8. A Modeling Framework for Network Processor Systems; Chapter 8. A Modeling Framework for Network Processor Systems; PART II: PRACTICES; PART II: PRACTICES; Chapter 9. An Industry Analyst's Perspective on Networ k Processors. Chapter 9. An Industry Analyst's Perspective on Networ k ProcessorsChapter 10. Agere Systems--Communications Optimized PayloadPlus Network Processor Architecture; Chapter 10. Agere Systems--Communications Optimized PayloadPlus Network Processor Architecture; Chapter 11. Cisco Systems-- Toaster 2; Chapter 11. Cisco Systems-- Toaster 2; Chapter 12. IBM--PowerNP Network Processor; Chapter 12. IBM--PowerNP Network Processor; Chapter 13. Intel Corporation--Intel IXP2400 Network Processor: A Second-Generation Intel NPU. Chapter 13. Intel Corporation--Intel IXP2400 Network Processor: A Second-Generation Intel NPUChapter 14. Motorola--C-5e Network Processor; Chapter 14. Motorola--C-5e Network Processor; Chapter 15. PMC-Sierra, Inc.-- ClassiPI; Chapter 15. PMC-Sierra, Inc.-- ClassiPI; Chapter 16. TranSwitch--ASPEN: Flexible Network Processing for Access Solutions; Chapter 16. TranSwitch--ASPEN: Flexible Network Processing for Access Solutions; Index; Index; About the Editors; About the Editors. Microprocessors. http://id.loc.gov/authorities/subjects/sh85084898 Application-specific integrated circuits. http://id.loc.gov/authorities/subjects/sh89004045 Computer networks Equipment and supplies. Circuits intégrés à la demande. COMPUTERS Logic Design. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh Application-specific integrated circuits fast Computer networks Equipment and supplies fast Microprocessors fast
subject_GND	http://id.loc.gov/authorities/subjects/sh85084898 http://id.loc.gov/authorities/subjects/sh89004045
title	Network processor design : issues and practices.
title_auth	Network processor design : issues and practices.
title_exact_search	Network processor design : issues and practices.
title_full	Network processor design : issues and practices. Volume 1 / edited by Patrick Crowley [and others].
title_fullStr	Network processor design : issues and practices. Volume 1 / edited by Patrick Crowley [and others].
title_full_unstemmed	Network processor design : issues and practices. Volume 1 / edited by Patrick Crowley [and others].
title_short	Network processor design :
title_sort	network processor design issues and practices
title_sub	issues and practices.
topic	Microprocessors. http://id.loc.gov/authorities/subjects/sh85084898 Application-specific integrated circuits. http://id.loc.gov/authorities/subjects/sh89004045 Computer networks Equipment and supplies. Circuits intégrés à la demande. COMPUTERS Logic Design. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits Logic. bisacsh TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. bisacsh Application-specific integrated circuits fast Computer networks Equipment and supplies fast Microprocessors fast
topic_facet	Microprocessors. Application-specific integrated circuits. Computer networks Equipment and supplies. Circuits intégrés à la demande. COMPUTERS Logic Design. TECHNOLOGY & ENGINEERING Electronics Circuits Logic. TECHNOLOGY & ENGINEERING Electronics Circuits VLSI & ULSI. Application-specific integrated circuits Computer networks Equipment and supplies Microprocessors
url	https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=241119
work_keys_str_mv	AT crowleypatrick networkprocessordesignissuesandpracticesvolume1 AT hadimiogluhaldun networkprocessordesignissuesandpracticesvolume1 AT onufrykpeterz networkprocessordesignissuesandpracticesvolume1

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