Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Cham
Springer International Publishing
2014
Cham Springer |
| Ausgabe: | 1st ed. 2014 |
| Schlagworte: | |
| Online-Zugang: | BTU01 FHA01 FHI01 FHN01 FHR01 FKE01 FRO01 FWS01 FWS02 UBY01 Volltext |
| Beschreibung: | 1 Online-Ressource (XVIII, 245 p. 133 illus., 115 illus. in color) |
| ISBN: | 9783319023786 |
| DOI: | 10.1007/978-3-319-02378-6 |
Internformat
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Datensatz im Suchindex
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| author | Noia, Brandon Chakrabarty, Krishnendu |
| author_facet | Noia, Brandon Chakrabarty, Krishnendu |
| author_role | aut aut |
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| collection | ZDB-2-ENG |
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| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
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| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-3-319-02378-6 |
| edition | 1st ed. 2014 |
| format | Electronic eBook |
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| id | DE-604.BV046083145 |
| illustrated | Not Illustrated |
| indexdate | 2024-08-01T10:55:48Z |
| institution | BVB |
| isbn | 9783319023786 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-031464202 |
| oclc_num | 868318202 |
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| owner_facet | DE-Aug4 DE-898 DE-BY-UBR DE-861 DE-573 DE-859 DE-634 DE-92 DE-706 DE-863 DE-BY-FWS DE-862 DE-BY-FWS |
| physical | 1 Online-Ressource (XVIII, 245 p. 133 illus., 115 illus. in color) |
| psigel | ZDB-2-ENG ZDB-2-ENG_2014_Fremddaten |
| publishDate | 2014 |
| publishDateSearch | 2014 |
| publishDateSort | 2014 |
| publisher | Springer International Publishing Springer |
| record_format | marc |
| spellingShingle | Noia, Brandon Chakrabarty, Krishnendu Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs Circuits and Systems Processor Architectures Semiconductors Systems engineering Computer science |
| title | Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs |
| title_auth | Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs |
| title_exact_search | Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs |
| title_full | Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs by Brandon Noia, Krishnendu Chakrabarty |
| title_fullStr | Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs by Brandon Noia, Krishnendu Chakrabarty |
| title_full_unstemmed | Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs by Brandon Noia, Krishnendu Chakrabarty |
| title_short | Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs |
| title_sort | design for test and test optimization techniques for tsv based 3d stacked ics |
| topic | Circuits and Systems Processor Architectures Semiconductors Systems engineering Computer science |
| topic_facet | Circuits and Systems Processor Architectures Semiconductors Systems engineering Computer science |
| url | https://doi.org/10.1007/978-3-319-02378-6 |
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