Proceedings of the 28th Annual International Symposium on Microarchitecture: November 29 - December 1, 1995 ; Ann Arbor, Michigan
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Los Alamitos, Calif. [u.a.]
IEEE Computer Soc. Press
1995
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XIV, 361 S. graph. Darst. |
| ISBN: | 0818673494 |
Internformat
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Datensatz im Suchindex
| _version_ | 1804125137264443392 |
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| adam_text | Proceedings of MICROS,
1995
Table of Contents
Preface
.........................................................................................................................................ix
Program and Steering Committees
........................................................................................xi
Referees
.....................................................................................................................................xiii
Keynote Address:
Richard I.
Baum -
IBM Fellow and Vice-President, Systems Architecture and Performance,
Systems Technology and Architecture Division
-
IBM, Austin
Branch Prediction I
Chair: Yale
N.
Patt
-
University of Michigan, Ann Arbor
Performance Issues in Correlated Branch Prediction Schemes
.....................................................3
N.
Gloy, M.D. Smith, and
С
Young
Dynamic Path-Based Branch Correlation
..................................................................................15
R. Nair
The Predictability of Branches in Libraries
...............................................................................24
B.
Calder,
D.
Grunwald,
and A. Srivastava
IIP Compilation I
Chair: Guang R.
Gao
-
McGill University
The Performance Impact of Incomplete Bypassing in Processor Pipelines
.................................36
P.S.
Ahuja,
D.W.
Clark, and A. Rogers
Efficient Instruction Scheduling Using Finite State Automata
...................................................46
V.
Bala
and
N.
Rubin
Critical Path Reduction for Scalar Programs
.............................................................................57
M. Schlansker and V. Kathail
Memory System Issues
Chair: Andrew Wolfe
-
Princeton University
A Limit Study of Local Memory Requirements Using Value Reuse Profiles
.............................71
A.S. Huang andJ.P. Shen
Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency
...............................82
T.M. Austin and G.S.
Sohi
A Modified Approach to Data Cache Management
...................................................................93
G. Tyson,
M. F
ärrens,
J.
Matthews, and
A. R. Pleszkun
Topics in Software
Pipelining and IIP Compilation
Chair: Bob Rau
-
Hewlett-Packard Laboratories, Palo Alto
Petri
Net versus Modulo Scheduling for Software Pipelining
..................................................105
V.H. Allan,
U.R.
Shah, and
K.M.
Ready
Modulo Scheduling with Multiple Initiation Intervals
..............................................................
Ill
N.J.
Warter-Perez andN. Partamian
Spill-Free Parallel Scheduling of Basic Blocks
........................................................................119
B. Natarajan and M. Schlansker
Improving Instruction-Level Parallelism by Loop Unrolling and Dynamic
Memory Disambiguation
........................................................................................................125
J. W. Davidson and S. Jinturkar
Invited speaker:
Thomas A. Jermoluk
-
President and Chief Operating Officer
-
Silicon Graphics, Inc.
Data How and Multithreading Architectures
Chair: Jean-Luc Gaudiot
-
University of Southern California
Self-Regulation of Workload in the Manchester Data-Flow Computer
....................................135
J.R. GurdandD.F.
Snelling
The M-Machine Multicomputer
..............................................................................................146
M.
Filio,
S.W.
Keckler, W.J. Dally, N.P. Carter, A. Chang, Y. Gurevich, and W.S. Lee
IIP Compilation II
Chair: James Dehnert
-
Silicon Graphics, Inc.
Region-Based Compilation: An Introduction and Motivation
.................................................158
R.E. Hank, W-M.W. Hwu, andB.R. Rau
An Experimental Study of Several Cooperative Register Allocation and Instruction
Scheduling Strategies
..............................................................................................................169
С
Noms
and
UL·
Pollock
Register Allocation for Predicated Code
.................................................................................180
A.E. Eichenberger and E.S. Davidson
Analysis of Branching Architecture
Chair: Edward S. Davidson
-
University of Michigan, Ann Arbor
Partial Resolution in Branch Target Buffers
............................................................................193
B. Fagin and K. Russell
A System-Level Perspective on Branch Architecture Performance
..........................................199
B. Colder, D.
Grunwald,
and J. Enter
vi
Software and Hardware Object Code Translation
Chair:
Wen-Mei W. Hwu
-
University of
Illinois, Urbana-Champaign
Dynamic Rescheduling: A Technique for Object Code Compatibility in VLIW
Architectures
..........................................................................................................................208
T.M.
Conte
and
S.W.
Sathaye
Improving CISC Instruction Decoding Performance Using a Fill Unit
.....................................219
M. Smotherman and M. Franklin
Data Prefetching
Chair: Gearold R. Johnson
-
National Technological University, Fort Collins
SPAID: Software Prefetching in Pointer- and Call-Intensive Environments
............................231
M.H. Lipasti, W.J. Schmidt, S.R.
Kunkel,
and R.R. Roediger
An Effective Programmable Prefetch Engine for On-Chip Caches
..........................................237
Т
-F.
Chen
Cache Miss Heuristics and Preloading Techniques for General-Purpose Programs
..................243
T. Ozawa, Y. Kimura, and S. Nishizaki
Panel: Design Directions for Future Processors
Organizer: James O.
Bondi
-
Texas Instruments, Dallas
Invited Speaker:
Fred J. Pollack
-
Intel Fellow and Director of Measurement, Architecture, and Planning,
Microprocessor Products group
—
Intel Corporation
Branch Prediction II
Chair: Robert P. Colwell
-
Intel,
Hillsboro
Alternative Implementations of Hybrid Branch Predictors
.......................................................252
P-Y. Chang, E. Hao, and Y.N.
Patt
Control Row Prediction with Tree-like Subgraphs for Superscalar Processors
........................258
S. Dutta and M. Franklin
The Role of Adaptivity in Two-Level Adaptive Branch Prediction
..........................................264
S.
Sechrest,
C-C.
Lee, and
T.
Mudge
Multithreading and Superscalar Design Studies
Chair: Hans Mulder
-
Intel, Santa Clara
Design of Storage Hierarchy in Multithreaded Architectures
...................................................271
L Roh
and W.A. Najjar
An Investigation of the Performance of Various Instruction-Issue Buffer Topologies
..............279
5.
Jourdan, P. Sainrat, and D. Litaize
Decoupling Integer Execution in Superscalar Processors
.........................................................285
S. Palacharla and J.E. Smith
vu
Architectural
Features
for ILP
Chair: Stephen W. Melvin
-
Zytek
Exploiting Short-Lived Variables in Superscalar Processors
....................................................292
LA. Lozano
and G.R.
Gao
Partitioned Register File for TTAs
..........................................................................................303
J.
Janssen
and H. Corporaal
Disjoint Eager Execution: An Optimal Form of Speculative Execution
..................................313
A.K. Uht and V. Sindagi
Software Pipelining II
Chair: Stanley
Habib
-
City University of New York
Unrolling-Based Optimizations for Modulo Scheduling
..........................................................327
D.M.
Lavery and W-M.W. Hwu
Stage Scheduling: A Technique to Reduce the Register Requirements of a Modulo
Schedule
.................................................................................................................................338
A.E. Eichenberger and E.S. Davidson
Hypernode Reduction Modulo Scheduling
..............................................................................350
J.
Llosa,
M.
Valero,
E. Ayguadé,
and A. Gonzalez
Author Index
.......................................................................................................................
36i
VUl
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| spelling | Micro 28 1995 Ann Arbor, Mich. Verfasser (DE-588)5172484-4 aut Proceedings of the 28th Annual International Symposium on Microarchitecture November 29 - December 1, 1995 ; Ann Arbor, Michigan [MICRO-28] MICRO-28 Los Alamitos, Calif. [u.a.] IEEE Computer Soc. Press 1995 XIV, 361 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Mikroarchitektur (DE-588)4139308-9 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1995 Ann Arbor Mich. gnd-content Mikroarchitektur (DE-588)4139308-9 s DE-604 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=007114386&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings of the 28th Annual International Symposium on Microarchitecture November 29 - December 1, 1995 ; Ann Arbor, Michigan Mikroarchitektur (DE-588)4139308-9 gnd |
| subject_GND | (DE-588)4139308-9 (DE-588)1071861417 |
| title | Proceedings of the 28th Annual International Symposium on Microarchitecture November 29 - December 1, 1995 ; Ann Arbor, Michigan |
| title_alt | MICRO-28 |
| title_auth | Proceedings of the 28th Annual International Symposium on Microarchitecture November 29 - December 1, 1995 ; Ann Arbor, Michigan |
| title_exact_search | Proceedings of the 28th Annual International Symposium on Microarchitecture November 29 - December 1, 1995 ; Ann Arbor, Michigan |
| title_full | Proceedings of the 28th Annual International Symposium on Microarchitecture November 29 - December 1, 1995 ; Ann Arbor, Michigan [MICRO-28] |
| title_fullStr | Proceedings of the 28th Annual International Symposium on Microarchitecture November 29 - December 1, 1995 ; Ann Arbor, Michigan [MICRO-28] |
| title_full_unstemmed | Proceedings of the 28th Annual International Symposium on Microarchitecture November 29 - December 1, 1995 ; Ann Arbor, Michigan [MICRO-28] |
| title_short | Proceedings of the 28th Annual International Symposium on Microarchitecture |
| title_sort | proceedings of the 28th annual international symposium on microarchitecture november 29 december 1 1995 ann arbor michigan |
| title_sub | November 29 - December 1, 1995 ; Ann Arbor, Michigan |
| topic | Mikroarchitektur (DE-588)4139308-9 gnd |
| topic_facet | Mikroarchitektur Konferenzschrift 1995 Ann Arbor Mich. |
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