Digital Timing Macromodeling for VLSI Design Verification:
Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level s...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1995
|
| Schriftenreihe: | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
319 |
| Schlagworte: | |
| Online-Zugang: | BTU01 URL des Erstveröffentlichers |
| Zusammenfassung: | Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques |
| Beschreibung: | 1 Online-Ressource (XXI, 265 p) |
| ISBN: | 9781461523215 |
| DOI: | 10.1007/978-1-4615-2321-5 |
Internformat
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| 520 | |a Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques | ||
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Datensatz im Suchindex
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| institution | BVB |
| isbn | 9781461523215 |
| language | English |
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| series2 | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
| spelling | Kong, Jeong-Taek Verfasser aut Digital Timing Macromodeling for VLSI Design Verification by Jeong-Taek Kong, David Overhauser Boston, MA Springer US 1995 1 Online-Ressource (XXI, 265 p) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 319 Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer-aided engineering Electrical engineering Electronic circuits Entwurf (DE-588)4121208-3 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s 1\p DE-604 Overhauser, David aut Erscheint auch als Druck-Ausgabe 9781461359821 https://doi.org/10.1007/978-1-4615-2321-5 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Kong, Jeong-Taek Overhauser, David Digital Timing Macromodeling for VLSI Design Verification Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer-aided engineering Electrical engineering Electronic circuits Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4121208-3 (DE-588)4117388-0 |
| title | Digital Timing Macromodeling for VLSI Design Verification |
| title_auth | Digital Timing Macromodeling for VLSI Design Verification |
| title_exact_search | Digital Timing Macromodeling for VLSI Design Verification |
| title_full | Digital Timing Macromodeling for VLSI Design Verification by Jeong-Taek Kong, David Overhauser |
| title_fullStr | Digital Timing Macromodeling for VLSI Design Verification by Jeong-Taek Kong, David Overhauser |
| title_full_unstemmed | Digital Timing Macromodeling for VLSI Design Verification by Jeong-Taek Kong, David Overhauser |
| title_short | Digital Timing Macromodeling for VLSI Design Verification |
| title_sort | digital timing macromodeling for vlsi design verification |
| topic | Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer-aided engineering Electrical engineering Electronic circuits Entwurf (DE-588)4121208-3 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer-aided engineering Electrical engineering Electronic circuits Entwurf VLSI |
| url | https://doi.org/10.1007/978-1-4615-2321-5 |
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