Logic Synthesis for VLSI-Based Combined Finite State Machines: Synthesis Targeting ASICs, CPLDs and FPGAs
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Cham
Springer International Publishing
2022
Cham Springer |
| Ausgabe: | 1st ed. 2022 |
| Schriftenreihe: | Lecture Notes in Electrical Engineering
922 |
| Schlagworte: | |
| Online-Zugang: | BTU01 FHA01 FHD01 FHI01 FHM01 FHN01 FHR01 FKE01 FLA01 FRO01 FWS01 FWS02 HTW01 UBA01 UBG01 UBM01 UBR01 UBT01 UBW01 UBY01 UEI01 UER01 UPA01 Volltext |
| Beschreibung: | 1 Online-Ressource (XV, 291 p. 270 illus) |
| ISBN: | 9783031160271 |
| ISSN: | 1876-1119 |
| DOI: | 10.1007/978-3-031-16027-1 |
Internformat
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Datensatz im Suchindex
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| author | Barkalov, Alexander Titarenko, Larysa Mielcarek, Kamil Mazurkiewicz, Małgorzata Kawecka, Elżbieta |
| author_facet | Barkalov, Alexander Titarenko, Larysa Mielcarek, Kamil Mazurkiewicz, Małgorzata Kawecka, Elżbieta |
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| author_sort | Barkalov, Alexander |
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| dewey-hundreds | 600 - Technology (Applied sciences) |
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| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-3-031-16027-1 |
| edition | 1st ed. 2022 |
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| illustrated | Not Illustrated |
| index_date | 2024-07-03T21:10:42Z |
| indexdate | 2024-08-01T10:56:12Z |
| institution | BVB |
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| physical | 1 Online-Ressource (XV, 291 p. 270 illus) |
| psigel | ZDB-2-SCS ZDB-2-SCS_2022 |
| publishDate | 2022 |
| publishDateSearch | 2022 |
| publishDateSort | 2022 |
| publisher | Springer International Publishing Springer |
| record_format | marc |
| series2 | Lecture Notes in Electrical Engineering |
| spellingShingle | Barkalov, Alexander Titarenko, Larysa Mielcarek, Kamil Mazurkiewicz, Małgorzata Kawecka, Elżbieta Logic Synthesis for VLSI-Based Combined Finite State Machines Synthesis Targeting ASICs, CPLDs and FPGAs Electronic Circuits and Systems Control and Systems Theory Electronic circuits Control engineering |
| title | Logic Synthesis for VLSI-Based Combined Finite State Machines Synthesis Targeting ASICs, CPLDs and FPGAs |
| title_auth | Logic Synthesis for VLSI-Based Combined Finite State Machines Synthesis Targeting ASICs, CPLDs and FPGAs |
| title_exact_search | Logic Synthesis for VLSI-Based Combined Finite State Machines Synthesis Targeting ASICs, CPLDs and FPGAs |
| title_exact_search_txtP | Logic Synthesis for VLSI-Based Combined Finite State Machines Synthesis Targeting ASICs, CPLDs and FPGAs |
| title_full | Logic Synthesis for VLSI-Based Combined Finite State Machines Synthesis Targeting ASICs, CPLDs and FPGAs by Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Małgorzata Mazurkiewicz, Elżbieta Kawecka |
| title_fullStr | Logic Synthesis for VLSI-Based Combined Finite State Machines Synthesis Targeting ASICs, CPLDs and FPGAs by Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Małgorzata Mazurkiewicz, Elżbieta Kawecka |
| title_full_unstemmed | Logic Synthesis for VLSI-Based Combined Finite State Machines Synthesis Targeting ASICs, CPLDs and FPGAs by Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Małgorzata Mazurkiewicz, Elżbieta Kawecka |
| title_short | Logic Synthesis for VLSI-Based Combined Finite State Machines |
| title_sort | logic synthesis for vlsi based combined finite state machines synthesis targeting asics cplds and fpgas |
| title_sub | Synthesis Targeting ASICs, CPLDs and FPGAs |
| topic | Electronic Circuits and Systems Control and Systems Theory Electronic circuits Control engineering |
| topic_facet | Electronic Circuits and Systems Control and Systems Theory Electronic circuits Control engineering |
| url | https://doi.org/10.1007/978-3-031-16027-1 |
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