VLSI 93: proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration ; Grenoble, France, 7 - 10 September, 1993
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | Undetermined |
| Veröffentlicht: |
Amsterdam u.a.
North-Holland
1994
|
| Schriftenreihe: | International Federation for Information Processing: [IFIP transactions / A]
42 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | IX, 364 S. Ill., graph. Darst. |
| ISBN: | 0444899111 |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV009657254 | ||
| 003 | DE-604 | ||
| 005 | 19951115 | ||
| 007 | t| | ||
| 008 | 940615s1994 xx ad|| |||| 10||| und d | ||
| 020 | |a 0444899111 |9 0-444-89911-1 | ||
| 035 | |a (OCoLC)844198524 | ||
| 035 | |a (DE-599)BVBBV009657254 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | |a und | ||
| 049 | |a DE-20 |a DE-384 |a DE-91G | ||
| 084 | |a ELT 355f |2 stub | ||
| 111 | 2 | |a International Conference on Very Large Scale Integration |n 7 |d 1993 |c Grenoble |j Verfasser |0 (DE-588)5102576-0 |4 aut | |
| 245 | 1 | 0 | |a VLSI 93 |b proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration ; Grenoble, France, 7 - 10 September, 1993 |c ed. by Takayuki Yanagawa ... |
| 264 | 1 | |a Amsterdam u.a. |b North-Holland |c 1994 | |
| 300 | |a IX, 364 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a International Federation for Information Processing: [IFIP transactions / A] |v 42 | |
| 650 | 0 | 7 | |a Digitaltechnik |0 (DE-588)4012303-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 1993 |z Grenoble |2 gnd-content | |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 1 | |a Digitaltechnik |0 (DE-588)4012303-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Yanagawa, Takayuki |e Sonstige |4 oth | |
| 810 | 2 | |a A] |t International Federation for Information Processing: [IFIP transactions |v 42 |w (DE-604)BV006188900 |9 42 | |
| 856 | 4 | 2 | |m Digitalisierung TU Muenchen |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006384913&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-006384913 | |
Datensatz im Suchindex
| _version_ | 1820868058527301632 |
|---|---|
| adam_text |
Contents
Keynote
The single chip system era
.3
J.
Borei,
J.
Monnier and G. Matheron
Layout Synthesis
Post-placement technology mapping
.15
D.
Brašen
and A. Ginetti
Optimal layout recycling based on graph theoretic linear
programming approach
.25
Y. Shigehiro, T. Nagata, I. Shirakawa and T. Kambe
A family of module generators for the layout synthesis of I/O buffers
.35
K.M.
Nguyen and M.C. Lefebvre
A
45°
compaction algorithm handling overconstraints
.45
L. Ladage and G.
Lodde
Special Purpose Architectures
Personal Communicators: A better way to stay in touch
.57
Invited
-
H. M.
Hauser
Design of a GaAs redundant divider
.63
I.
Moussa,
A. Skaf
and A. Guyot
An ASIC array architecture for the DITPOS algorithm
.73
P.M.R. Jensen
Performance of object caching for object-oriented systems
.83
J.M. Chang and E.F.
Gehringer
A VLSI circuit for on-line polynomial computing: Application to exponential,
trigonometric and hyperbolic functions
.93
A. Skaf,
J.-C. Bajard, A. Guyot and J.-M.
Muller
Design For Testability
Self-parity combinational circuits for self-testing, concurrent fault detection
and parity scan design
.103
M.
Gossel
and E.-S. Sogomonyan
Partitioning and hierarchical description of self-testable designs
. 113
A.P. Stroele
Test of single fault tolerant controllers in VLSI circuits
. 123
R. Leveugle
A C-testable parallel multiplier using differential cascode voltage switch
(DCVS) logic
.
133
W.AJ. Waller and S.M. Aziz
Image Processing
Opportunities for integrating early-vision computation algorithms and
VLSI technology to the development of smart sensors
. 145
Invited
-
D. Poussart
Single board image processing unit for vehicle guidance
. 151
J.
Schönfeld
and P.
Pirsch
Implementation of the volume rendering algorithm using a
low-power design-style
.161
J.
Smit,
M.J. Bentum and M.M. Samsom
Design of a dedicated neural network on silicon: application to
optical character recognition
.169
D.
Jacquet
and G. Saucier
High Performance Processors
ARM6: Processor design for high performance at low power
. 181
Invited
-
M.
Muller
A new method for retiming multi-functional processing units
. 191
A. Van
der Werf,
E.H.L.
Aarts,
E.W.
Heìjnen,
J.L.
Van Meerbergen,
W.F
J. Verhaegh and P.E.R.
Lippens
A transformational approach to asynchronous high-level synthesis
. 201
G. Gopalakrishnan and V. Akella
A micropipelined ARM
.211
S.B. Furber, P. Day, J.D. Garside, N.C. Paver and J.V. Woods
A high performance RISC microprocessor
.221
F. Poirier,
J.C.
Heudin,
M.
Belleville and
С
Jaffard
Low Level Models
Probabilistic power consumption estimation in digital circuits
. 231
W.
Röthig, E.
Melcher and M. Dana
їх
Solving the partial differential equations of transmission lines with
wave digital filters
.241
M. Erbar, I.
Kőnenkamp
and E.-H. Horneber
Parallel harmonic balance
.251
M. Schneider, U.
Wever
and Q. Zheng
Estimating lower hardware bounds in high-level synthesis
. 261
N.
Wehn, M. Glesner and
С
Vielhauer
Multichip Modules
Ultra high speed CMOS design
.273
Invited-
C. Svensson
and J. Yuan
The implementation of a MCM associative string processor
. 283
CM. Habiger and I.P. Jalowiecki
Superconductive interconnections in multi-chip modules
. 291
B. Cabon, T.V. Dinh and J.
Chilo
Routing
A multilayer channel router based on optimal multilayer net assignment
. 301
M.S. Tanaka and M. Ishikawa
The chaos router chip: design and implementation of an adaptive router
. 311
K.
Bolding,
S.-C. Cheung, S.-E. Choi,
С
Ebeling,
S. Hassoun, T.A. Ngo and R.
Wille
A new performance-driven global routing algorithm for gate array
. 321
T. Xue, T.
Fujii
and E.S.
Kuh
Simulation
Circuit simulation for large interconnected
1С
networks
. 333
S. Lin and E.S.
Kuh
Bondgraph
execution as a new algorithm for circuit simulation
. 343
M.
Müller
Adaptive checkpoint intervals in an optimistically synchronised parallel
digital system simulator
.353
A.C.
Palaniswamy and
P.A.
Wilsey
Author Index
.363 |
| any_adam_object | 1 |
| author_corporate | International Conference on Very Large Scale Integration Grenoble |
| author_corporate_role | aut |
| author_facet | International Conference on Very Large Scale Integration Grenoble |
| author_sort | International Conference on Very Large Scale Integration Grenoble |
| building | Verbundindex |
| bvnumber | BV009657254 |
| classification_rvk | SS 1993 |
| classification_tum | ELT 355f |
| ctrlnum | (OCoLC)844198524 (DE-599)BVBBV009657254 |
| discipline | Elektrotechnik |
| format | Conference Proceeding Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a2200000 cb4500</leader><controlfield tag="001">BV009657254</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">19951115</controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">940615s1994 xx ad|| |||| 10||| und d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0444899111</subfield><subfield code="9">0-444-89911-1</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)844198524</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV009657254</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">und</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-20</subfield><subfield code="a">DE-384</subfield><subfield code="a">DE-91G</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 355f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="111" ind1="2" ind2=" "><subfield code="a">International Conference on Very Large Scale Integration</subfield><subfield code="n">7</subfield><subfield code="d">1993</subfield><subfield code="c">Grenoble</subfield><subfield code="j">Verfasser</subfield><subfield code="0">(DE-588)5102576-0</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">VLSI 93</subfield><subfield code="b">proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration ; Grenoble, France, 7 - 10 September, 1993</subfield><subfield code="c">ed. by Takayuki Yanagawa ...</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Amsterdam u.a.</subfield><subfield code="b">North-Holland</subfield><subfield code="c">1994</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">IX, 364 S.</subfield><subfield code="b">Ill., graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">International Federation for Information Processing: [IFIP transactions / A]</subfield><subfield code="v">42</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitaltechnik</subfield><subfield code="0">(DE-588)4012303-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)1071861417</subfield><subfield code="a">Konferenzschrift</subfield><subfield code="y">1993</subfield><subfield code="z">Grenoble</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Digitaltechnik</subfield><subfield code="0">(DE-588)4012303-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Yanagawa, Takayuki</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="810" ind1="2" ind2=" "><subfield code="a">A]</subfield><subfield code="t">International Federation for Information Processing: [IFIP transactions</subfield><subfield code="v">42</subfield><subfield code="w">(DE-604)BV006188900</subfield><subfield code="9">42</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Digitalisierung TU Muenchen</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006384913&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-006384913</subfield></datafield></record></collection> |
| genre | (DE-588)1071861417 Konferenzschrift 1993 Grenoble gnd-content |
| genre_facet | Konferenzschrift 1993 Grenoble |
| id | DE-604.BV009657254 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T13:18:20Z |
| institution | BVB |
| institution_GND | (DE-588)5102576-0 |
| isbn | 0444899111 |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-006384913 |
| oclc_num | 844198524 |
| open_access_boolean | |
| owner | DE-20 DE-384 DE-91G DE-BY-TUM |
| owner_facet | DE-20 DE-384 DE-91G DE-BY-TUM |
| physical | IX, 364 S. Ill., graph. Darst. |
| publishDate | 1994 |
| publishDateSearch | 1994 |
| publishDateSort | 1994 |
| publisher | North-Holland |
| record_format | marc |
| series2 | International Federation for Information Processing: [IFIP transactions / A] |
| spelling | International Conference on Very Large Scale Integration 7 1993 Grenoble Verfasser (DE-588)5102576-0 aut VLSI 93 proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration ; Grenoble, France, 7 - 10 September, 1993 ed. by Takayuki Yanagawa ... Amsterdam u.a. North-Holland 1994 IX, 364 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier International Federation for Information Processing: [IFIP transactions / A] 42 Digitaltechnik (DE-588)4012303-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1993 Grenoble gnd-content VLSI (DE-588)4117388-0 s Digitaltechnik (DE-588)4012303-0 s DE-604 Yanagawa, Takayuki Sonstige oth A] International Federation for Information Processing: [IFIP transactions 42 (DE-604)BV006188900 42 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006384913&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | VLSI 93 proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration ; Grenoble, France, 7 - 10 September, 1993 Digitaltechnik (DE-588)4012303-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4012303-0 (DE-588)4117388-0 (DE-588)1071861417 |
| title | VLSI 93 proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration ; Grenoble, France, 7 - 10 September, 1993 |
| title_auth | VLSI 93 proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration ; Grenoble, France, 7 - 10 September, 1993 |
| title_exact_search | VLSI 93 proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration ; Grenoble, France, 7 - 10 September, 1993 |
| title_full | VLSI 93 proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration ; Grenoble, France, 7 - 10 September, 1993 ed. by Takayuki Yanagawa ... |
| title_fullStr | VLSI 93 proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration ; Grenoble, France, 7 - 10 September, 1993 ed. by Takayuki Yanagawa ... |
| title_full_unstemmed | VLSI 93 proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration ; Grenoble, France, 7 - 10 September, 1993 ed. by Takayuki Yanagawa ... |
| title_short | VLSI 93 |
| title_sort | vlsi 93 proceedings of the ifip tc10 wg10 5 international conference on very large scale integration grenoble france 7 10 september 1993 |
| title_sub | proceedings of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration ; Grenoble, France, 7 - 10 September, 1993 |
| topic | Digitaltechnik (DE-588)4012303-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Digitaltechnik VLSI Konferenzschrift 1993 Grenoble |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=006384913&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV006188900 |
| work_keys_str_mv | AT internationalconferenceonverylargescaleintegrationgrenoble vlsi93proceedingsoftheifiptc10wg105internationalconferenceonverylargescaleintegrationgrenoblefrance710september1993 AT yanagawatakayuki vlsi93proceedingsoftheifiptc10wg105internationalconferenceonverylargescaleintegrationgrenoblefrance710september1993 |