Approaches to code generation for synchronous transfer architecture (STA):
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
Aachen
Shaker
2008
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| Schriftenreihe: | Berichte aus der Informatik
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XIII, 224 S. graph. Darst. 21 cm |
| ISBN: | 9783832276157 |
Internformat
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Datensatz im Suchindex
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| adam_text | CONTENTS LIST OF FIGURES VII LIST OF TABLES X ABBREVIATIONS XU 1
INTRODUCTION 1 1.1 BACKGROUND AND PROBLEMS 1 1.2 CODE GENERATION FOR STA
2 1.3 OBJECTIVES OF THIS THESIS 3 1.4 OUTLINE 3 2 CONCEPTS OF CODE
GENERATION 5 2.1 COMPILATION PHASES 5 2.2 CODE GENERATION 11 2.2.1
INSTRUCTION SELECTION 11 2.2.2 REGISTER ALLOCATION AND ASSIGNMENT 13
2.2.3 INSTRUCTION SCHEDULING 15 3 CODE GENERATION FOR SYNCHRONOUS
TRANSFER ARCHITECTURE 20 3.1 CODE GENERATION FOR DIGITAL SIGNAL
PROCESSORS 22 3.2 SYNCHRONOUS TRANSFER ARCHITECTURE (STA) 23 3.3 CODE
GENERATION FOR STA 25 3.4 INTEGRATED CODE GENERATION 26 3.4.1 PHASE
COUPLING PROBLEM 26 3.4.2 RELATED WORK 28 3.4.3 OVERVIEW OF MY STUDIES
29 GESCANNT DURCH BIBLIOGRAFISCHE INFORMATIONEN
HTTP://D-NB.INFO/990963403 DIGITALISIERT DURCH * * * * 8.3.4 CAUING
CONVENTIONS 145 CONTENTS INTEGRATED CODE GENERATION USING GREEDY
ALGORITHMS 95 6.1 INTRODUCTION 95 6.2 MATHEMATICAL FOUNDATIONS 96 6.2.1
COMBINATORIAL OPTIMIZATION 96 6.2.2 MINIMUM SPANNING TREE (MST) PROBLEM
96 6.2.3 KNAPSACK PROBLEM 99 6.3 CODE GENERATION BASED ON GREEDY
ALGORITHMS 99 6.3.1 INSTRUCTION SCHEDULING MODELED AS MST PROBLEM 100
6.3.2 REGISTER ALLOCATION MODELED AS KNAPSACK PROBLEM 103 6.4
EXPERIMENTAL RESULTS 105 6.4.1 TESTING AND RESULTS 105 6.4.2 DISCUSSION
AND SUMMARY 107 DISCUSSION OF THREE INTEGRATED APPROACHES 109 7.1
EXPERIMENTAL ENVIRONMENT 109 7.1.1 COMPILER CONSTRUCTION 109 7.1.2
SAMTRA ARCHITECTURE 111 7.2 COMPARISON OF CODE PERFORMANCE 112 7.2.1
CODESIZE 112 7.2.2 EXECUTION SPEED 113 7.2.3 COMPILATION TIME 113 7.2.4
REGISTER CONSUMPTION 114 7.2.5 MEMORY AND REGISTER ACCESS 115 7.3
DISCUSSION AND SUMMARY 116 COSY COMPILER ON STA 119 8.1 BASICS OF COSY
119 8.1.1 CCMIR 120 8.1.2 ENGINES 123 8.1.3 BEG 124 8.2 FEATURES OF
SIOUX ARCHITECTURE 126 8.3 THE IMPLEMENTATION OF OUR CODE GENERATOR 130
8.3.1 REALIZATION OF STA DIRECT DATA ROUTING 130 8.3.2 THE SCHEDULER 136
8.3.3 THERULES 139 D.2.4 DECODER UNIT 208 CONTENTS 8.4 EXPERIMENTAL
RESULTS 146 8.4.1 TESTING AND RESULTS 148 8.4.2 DISCUSSION AND SUMMARY
150 9 CONCLUSIONS 151 A SOLVING LP PROBLEM USING GLPK 155 A.L LP PROBLEM
155 A.2 LP MODEL 155 A.3 RESULTS USING GLPK 156 B INSTRUCTION SET
ARCHITECTURE OF THE SAMIRA 158 B.L SAMIRA CORE 158 B.2 INSTRUCTION SET
ARCHITECTURE 158 B.2.1 SCALARUNITS 158 B.2.2 VECTOR UNITS 159 B.2.3
DECODER UNIT 159 B.2.4 SEQUENCING UNITS 159 B.2.5 INTER-CONNECTION UNIT
(ICU) 159 B.2.6 GENERAL-PURPOSE REGISTERS 160 C BENCHMARKS FOR THE
MATLAB COMPILER 165 C.L INTRODUCTION 165 C.2 FIR 165 C.3 IIR 169 C.4 LMS
171 C.5 CONVOLUTION 180 C.6 FFT 181 C.7 DCT 191 D INSTRUCTION SET
ARCHITECTURE OF THE SIOUX 20T D.L SIOUX CORE 207 D.2 INSTRUCTION SET
ARCHITECTURE 207 D.2.1 COMPUTATION UNITS 207 D.2.2 GENERAL-PURPOSE
REGISTERS 207 D.2.3 ADDRESSING UNITS 208 CONTENTS D.2.5 SEQUENCING UNITS
209 D.2.6 MEMORY LOAD/STORE UNIT 209 BIBLIOGRAPHY 209
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| author | Guo, Jie 1978- |
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| ctrlnum | (OCoLC)297564145 (DE-599)DNB990963403 |
| dewey-full | 004.220285545 |
| dewey-hundreds | 000 - Computer science, information, general works |
| dewey-ones | 004 - Computer science |
| dewey-raw | 004.220285545 |
| dewey-search | 004.220285545 |
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| discipline | Informatik |
| format | Thesis Book |
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| illustrated | Illustrated |
| indexdate | 2024-07-09T21:35:34Z |
| institution | BVB |
| isbn | 9783832276157 |
| language | English |
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| physical | XIII, 224 S. graph. Darst. 21 cm |
| publishDate | 2008 |
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| spelling | Guo, Jie 1978- Verfasser (DE-588)136627293 aut Approaches to code generation for synchronous transfer architecture (STA) Jie Guo Aachen Shaker 2008 XIII, 224 S. graph. Darst. 21 cm txt rdacontent n rdamedia nc rdacarrier Berichte aus der Informatik Zugl.: Dresden, Techn. Univ., Diss., 2008 Computerarchitektur - Synchrone Übertragung - Codegenerierung - Optimierender Compiler Optimierender Compiler (DE-588)4342511-2 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Codegenerierung (DE-588)4010346-8 gnd rswk-swf Synchrone Übertragung (DE-588)7638167-5 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Computerarchitektur (DE-588)4048717-9 s Synchrone Übertragung (DE-588)7638167-5 s Codegenerierung (DE-588)4010346-8 s Optimierender Compiler (DE-588)4342511-2 s DE-604 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017371212&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Guo, Jie 1978- Approaches to code generation for synchronous transfer architecture (STA) Computerarchitektur - Synchrone Übertragung - Codegenerierung - Optimierender Compiler Optimierender Compiler (DE-588)4342511-2 gnd Computerarchitektur (DE-588)4048717-9 gnd Codegenerierung (DE-588)4010346-8 gnd Synchrone Übertragung (DE-588)7638167-5 gnd |
| subject_GND | (DE-588)4342511-2 (DE-588)4048717-9 (DE-588)4010346-8 (DE-588)7638167-5 (DE-588)4113937-9 |
| title | Approaches to code generation for synchronous transfer architecture (STA) |
| title_auth | Approaches to code generation for synchronous transfer architecture (STA) |
| title_exact_search | Approaches to code generation for synchronous transfer architecture (STA) |
| title_full | Approaches to code generation for synchronous transfer architecture (STA) Jie Guo |
| title_fullStr | Approaches to code generation for synchronous transfer architecture (STA) Jie Guo |
| title_full_unstemmed | Approaches to code generation for synchronous transfer architecture (STA) Jie Guo |
| title_short | Approaches to code generation for synchronous transfer architecture (STA) |
| title_sort | approaches to code generation for synchronous transfer architecture sta |
| topic | Computerarchitektur - Synchrone Übertragung - Codegenerierung - Optimierender Compiler Optimierender Compiler (DE-588)4342511-2 gnd Computerarchitektur (DE-588)4048717-9 gnd Codegenerierung (DE-588)4010346-8 gnd Synchrone Übertragung (DE-588)7638167-5 gnd |
| topic_facet | Computerarchitektur - Synchrone Übertragung - Codegenerierung - Optimierender Compiler Optimierender Compiler Computerarchitektur Codegenerierung Synchrone Übertragung Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017371212&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT guojie approachestocodegenerationforsynchronoustransferarchitecturesta |