Dual-loop gate drivers with analog and digital slope shaping:
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
Hannover
2019
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis Inhaltsverzeichnis |
| Beschreibung: | XII, 174 Seiten Illustrationen, Diagramme 30 cm |
Internformat
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| 100 | 1 | |a Gröger, Johannes Matthias |d 1986- |e Verfasser |0 (DE-588)1200998529 |4 aut | |
| 245 | 1 | 0 | |a Dual-loop gate drivers with analog and digital slope shaping |c von Johannes Matthias Gröger, M. Sc. |
| 264 | 1 | |a Hannover |c 2019 | |
| 300 | |a XII, 174 Seiten |b Illustrationen, Diagramme |c 30 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 502 | |b Dissertation |c Gottfried Wilhelm Leibniz Universität Hannover |d 2019 | ||
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Datensatz im Suchindex
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|---|---|
| adam_text | CONTENTS
CONTENTS
1 INTRODUCTION 1
1.1 INTRODUCTION. 1
1.2 SCOPE OF THIS WORK. 3
1.3 CONTRIBUTION OF THIS WORK. 4
1.4 OUTLINE . 7
2 FUNDAMENTALS 9
2.1 DEVICES AND CIRCUITS IN POWER ELECTRONICS. 9
2.1.1 MODEM GENERATION POWER SEMICONDUCTOR DEVICES. 9
2.1.2 HALF-BRIDGE CIRCUITS IN ELECTRICAL CONVERTERS. 10
2.2 SWITCHING BEHAVIOR OF GATE-CONTROLLED DEVICES. 11
2.2.1 EQUIVALENT CIRCUIT FOR THE SWITCHING DYNAMICS. 11
2.2.2 TUM-ON SWITCHING BEHAVIOR. 13
2.2.3 TURN-OFF SWITCHING BEHAVIOR. 16
2.2.4 TRADE-OFFS RESULTING FROM THE SLEW RATES OF THE SWITCHING
TRANSIENTS. 18
2.3 STATE-OF-THE-ART GATE DRIVE CONCEPTS . 24
2.3.1 PASSIVE GATE DRIVERS. 25
2.3.2 ACTIVE GATE DRIVERS WITH OPEN-LOOP SLOPE SHAPING. 27
2.3.3 ACTIVE GATE DRIVERS WITH CLOSED-LOOP SLOPE SHAPING . 28
3 THE DUAL-LOOP GATE DRIVER CONCEPT 33
3.1 INTRODUCTION. 33
3.2 THE ANALOG LOOP CONCEPT. 34
3.3 MODELING AND ANALYSIS. 36
3.3.1 SMALL-SIGNAL MODELING OF THE GATE DRIVER. 36
3.3.2 SMALL-SIGNAL STABILITY ANALYSIS . 39
3.3.3 LARGE SIGNAL TRANSIENT DOMAIN ANALYSIS . 43
IX
BIBLIOGRAFISCHE INFORMATIONEN
HTTP://D-NB.INFO/1206348143
CONTENTS
3.4 OPTIMIZED DV^/DZ, D/C/D/ SENSING. 44
3.4.1 DVCE/DT AND D/C/DZ SENSING. 46
3.4.2 INFLUENCES OF PARASITICS IN DVCE/DZ SENSING... 47
3.4.3 INFLUENCES OF PARASITICS IN D/C/DZ SENSING.. . . . YY. 50
3.4.4 OPTIMIZED SETUP. 52
3.5 THE DIGITAL LOOP CONCEPT . 54
3.6 SYSTEM REQUIREMENTS. 55
4 ANALOG LOOP DESIGN AND EVALUATION 59
4.1 DRIVER STAGE DESIGN. 59
4.1.1 REQUIREMENT ANALYSIS. 59
4.1.2 GENERAL APPROACHES AND CONCEPTS. 61
4.1.3 CONCEPT EVALUATION. 62
4.1.4 CONCEPT OF A COMMON-SOURCE DRIVER STAGE. 64
4.2 ANTI-WINDUP METHOD TO PREVENT NON-LINEARITIES . 69
4.3 DESIGN OF THE D/C/DZ FEEDBACK. 75
4.3.1 REQUIREMENT ANALYSIS. 75
4.3.2 CONCEPT EVALUATION. 76
4.3.3 DESIGN AND SIMULATION RESULTS .. 77
4.4 SYSTEM SIMULATION SETUP AND INFLUENCE OF PARASITICS. 79
4.5 TRANSIENT STABILITY ANALYSIS. 82
4.5.1 TEST BENCH FOR THE STABILITY ANALYSIS. 82
4.5.2 ANALYSIS OF THE D/C/DZ AND DVCE/DZ CONTROL LOOP. 83
4.5.3 STABILITY IMPROVEMENT FOR THE D/C/DZ AND DVCE/DZ CONTROL LOOP. 85
4.5.4 ANALYSIS OF THE ANTI-WINDUP CONTROL LOOP. 88
4.6 SLOPE SHAPING. 89
4.7 COMPARISON WITH PASSIVE GATE DRIVERS. 92
4.7.1 RESISTIVE GATE DRIVER. 94
4.7.2 RC-COMPENSATED GATE DRIVER. 95
5 COMBINED DIGITAL AND ANALOG DUAL-LOOP SLOPE SHAPING 97
5.1 INTRODUCTION AND SYSTEM OVERVIEW. 97
5.2 ANALOG LOOP. 98
5.2.1 ANALOG LOOP HARDWARE CONCEPT. 98
5.2.2 REFERENCE CURRENT SOURCE. 99
5.2.3 DVCE/DZ FEEDBACK. 101
X
CONTENTS
5.2.4 D/C/DT FEEDBACK. 101
5.2.5 BASE-EMITTER FORWARD VOLTAGE COMPENSATION. 102
5.2.6 DRIVER STAGE . 103
5.3 DIGITAL LOOP. 104
5.3.1 OPERATING PRINCIPLE. 105
5.3.2 ANALOG-TO-DIGITAL CONVERTER (ADC). 106
5.3.3 FIELD-PROGRAMMABLE GATE ARRAY (FPGA). 108
5.3.4 GATE DRIVER ISOLATION. 109
5.3.5 DIGITAL-TO-ANALOG CONVERTER (DAC). ILL
5.3.6 DAC OUTPUT AMPLIFIER. 114
5.3.7 SUMMARY. 116
5.4 HARDWARE VERIFICATION. 117
5.4.1 HARDWARE EVALUATION MODULE . 117
5.4.2 MEASUREMENT SETUP. 118
5.4.3 SLEW RATE CONTROL PERFORMANCE. 120
5.4.4 COMPARISON WITH A PASSIVE GATE DRIVER. 120
5.4.5 COMPARISON OF DIFFERENT POWER SEMICONDUCTOR DEVICES. 122
5.4.6 SUMMARY. 126
6 CONCLUSION AND OUTLOOK 127
6.1 CONCLUSION . 127
6.2 OUTLOOK. 129
BIBLIOGRAPHY 131
LIST OF ABBREVIATIONS 143
LIST OF SYMBOLS 147
LIST OF FIGURES 151
LIST OF TABLES 157
APPENDIX 159
A ADDITIONAL RESULTS . 159
A.L ADDITIONAL RESULTS CLASS AB SOURCE-FOLLOWER. 159
A.2 ADDITIONAL RESULTS D/C/DR FEEDBACK. 162
A.3 ADDITIONAL RESULTS SYSTEM SIMULATION. 163
XI
CONTENTS
B SPI INTERFACE . 166
LIST OF PUBLICATIONS, PATENTS, PRESENTATIONS 168
LIST OF STUDENT THESES SUPERVISED BY THE AUTHOR
171
ABOUT THE AUTHOR
173
XII
|
| adam_txt |
CONTENTS
CONTENTS
1 INTRODUCTION 1
1.1 INTRODUCTION. 1
1.2 SCOPE OF THIS WORK. 3
1.3 CONTRIBUTION OF THIS WORK. 4
1.4 OUTLINE . 7
2 FUNDAMENTALS 9
2.1 DEVICES AND CIRCUITS IN POWER ELECTRONICS. 9
2.1.1 MODEM GENERATION POWER SEMICONDUCTOR DEVICES. 9
2.1.2 HALF-BRIDGE CIRCUITS IN ELECTRICAL CONVERTERS. 10
2.2 SWITCHING BEHAVIOR OF GATE-CONTROLLED DEVICES. 11
2.2.1 EQUIVALENT CIRCUIT FOR THE SWITCHING DYNAMICS. 11
2.2.2 TUM-ON SWITCHING BEHAVIOR. 13
2.2.3 TURN-OFF SWITCHING BEHAVIOR. 16
2.2.4 TRADE-OFFS RESULTING FROM THE SLEW RATES OF THE SWITCHING
TRANSIENTS. 18
2.3 STATE-OF-THE-ART GATE DRIVE CONCEPTS . 24
2.3.1 PASSIVE GATE DRIVERS. 25
2.3.2 ACTIVE GATE DRIVERS WITH OPEN-LOOP SLOPE SHAPING. 27
2.3.3 ACTIVE GATE DRIVERS WITH CLOSED-LOOP SLOPE SHAPING . 28
3 THE DUAL-LOOP GATE DRIVER CONCEPT 33
3.1 INTRODUCTION. 33
3.2 THE ANALOG LOOP CONCEPT. 34
3.3 MODELING AND ANALYSIS. 36
3.3.1 SMALL-SIGNAL MODELING OF THE GATE DRIVER. 36
3.3.2 SMALL-SIGNAL STABILITY ANALYSIS . 39
3.3.3 LARGE SIGNAL TRANSIENT DOMAIN ANALYSIS . 43
IX
BIBLIOGRAFISCHE INFORMATIONEN
HTTP://D-NB.INFO/1206348143
CONTENTS
3.4 OPTIMIZED DV^/DZ, D/C/D/ SENSING. 44
3.4.1 DVCE/DT AND D/C/DZ SENSING. 46
3.4.2 INFLUENCES OF PARASITICS IN DVCE/DZ SENSING. 47
3.4.3 INFLUENCES OF PARASITICS IN D/C/DZ SENSING.'. . . YY. 50
3.4.4 OPTIMIZED SETUP. 52
3.5 THE DIGITAL LOOP CONCEPT . 54
3.6 SYSTEM REQUIREMENTS. 55
4 ANALOG LOOP DESIGN AND EVALUATION " 59
4.1 DRIVER STAGE DESIGN. 59
4.1.1 REQUIREMENT ANALYSIS. 59
4.1.2 GENERAL APPROACHES AND CONCEPTS. 61
4.1.3 CONCEPT EVALUATION. 62
4.1.4 CONCEPT OF A COMMON-SOURCE DRIVER STAGE. 64
4.2 ANTI-WINDUP METHOD TO PREVENT NON-LINEARITIES . 69
4.3 DESIGN OF THE D/C/DZ FEEDBACK. 75
4.3.1 REQUIREMENT ANALYSIS. 75
4.3.2 CONCEPT EVALUATION. 76
4.3.3 DESIGN AND SIMULATION RESULTS . 77
4.4 SYSTEM SIMULATION SETUP AND INFLUENCE OF PARASITICS. 79
4.5 TRANSIENT STABILITY ANALYSIS. 82
4.5.1 TEST BENCH FOR THE STABILITY ANALYSIS. 82
4.5.2 ANALYSIS OF THE D/C/DZ AND DVCE/DZ CONTROL LOOP. 83
4.5.3 STABILITY IMPROVEMENT FOR THE D/C/DZ AND DVCE/DZ CONTROL LOOP. 85
4.5.4 ANALYSIS OF THE ANTI-WINDUP CONTROL LOOP. 88
4.6 SLOPE SHAPING. 89
4.7 COMPARISON WITH PASSIVE GATE DRIVERS. 92
4.7.1 RESISTIVE GATE DRIVER. 94
4.7.2 RC-COMPENSATED GATE DRIVER. 95
5 COMBINED DIGITAL AND ANALOG DUAL-LOOP SLOPE SHAPING 97
5.1 INTRODUCTION AND SYSTEM OVERVIEW. 97
5.2 ANALOG LOOP. 98
5.2.1 ANALOG LOOP HARDWARE CONCEPT. 98
5.2.2 REFERENCE CURRENT SOURCE. 99
5.2.3 DVCE/DZ FEEDBACK. 101
X
CONTENTS
5.2.4 D/C/DT FEEDBACK. 101
5.2.5 BASE-EMITTER FORWARD VOLTAGE COMPENSATION. 102
5.2.6 DRIVER STAGE . 103
5.3 DIGITAL LOOP. 104
5.3.1 OPERATING PRINCIPLE. 105
5.3.2 ANALOG-TO-DIGITAL CONVERTER (ADC). 106
5.3.3 FIELD-PROGRAMMABLE GATE ARRAY (FPGA). 108
5.3.4 GATE DRIVER ISOLATION. 109
5.3.5 DIGITAL-TO-ANALOG CONVERTER (DAC). ILL
5.3.6 DAC OUTPUT AMPLIFIER. 114
5.3.7 SUMMARY. 116
5.4 HARDWARE VERIFICATION. 117
5.4.1 HARDWARE EVALUATION MODULE . 117
5.4.2 MEASUREMENT SETUP. 118
5.4.3 SLEW RATE CONTROL PERFORMANCE. 120
5.4.4 COMPARISON WITH A PASSIVE GATE DRIVER. 120
5.4.5 COMPARISON OF DIFFERENT POWER SEMICONDUCTOR DEVICES. 122
5.4.6 SUMMARY. 126
6 CONCLUSION AND OUTLOOK 127
6.1 CONCLUSION . 127
6.2 OUTLOOK. 129
BIBLIOGRAPHY 131
LIST OF ABBREVIATIONS 143
LIST OF SYMBOLS 147
LIST OF FIGURES 151
LIST OF TABLES 157
APPENDIX 159
A ADDITIONAL RESULTS . 159
A.L ADDITIONAL RESULTS CLASS AB SOURCE-FOLLOWER. 159
A.2 ADDITIONAL RESULTS D/C/DR FEEDBACK. 162
A.3 ADDITIONAL RESULTS SYSTEM SIMULATION. 163
XI
CONTENTS
B SPI INTERFACE . 166
LIST OF PUBLICATIONS, PATENTS, PRESENTATIONS 168
LIST OF STUDENT THESES SUPERVISED BY THE AUTHOR
171
ABOUT THE AUTHOR
173
XII |
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| index_date | 2024-07-03T16:48:19Z |
| indexdate | 2024-07-10T09:05:13Z |
| institution | BVB |
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| physical | XII, 174 Seiten Illustrationen, Diagramme 30 cm |
| publishDate | 2019 |
| publishDateSearch | 2019 |
| publishDateSort | 2019 |
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| spelling | Gröger, Johannes Matthias 1986- Verfasser (DE-588)1200998529 aut Dual-loop gate drivers with analog and digital slope shaping von Johannes Matthias Gröger, M. Sc. Hannover 2019 XII, 174 Seiten Illustrationen, Diagramme 30 cm txt rdacontent n rdamedia nc rdacarrier Dissertation Gottfried Wilhelm Leibniz Universität Hannover 2019 Mehrfachregelung (DE-588)7649005-1 gnd rswk-swf Schaltregler (DE-588)4179380-8 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Schaltregler (DE-588)4179380-8 s Mehrfachregelung (DE-588)7649005-1 s DE-604 B:DE-101 application/pdf https://d-nb.info/1206348143/04 Inhaltsverzeichnis DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=032597438&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Gröger, Johannes Matthias 1986- Dual-loop gate drivers with analog and digital slope shaping Mehrfachregelung (DE-588)7649005-1 gnd Schaltregler (DE-588)4179380-8 gnd |
| subject_GND | (DE-588)7649005-1 (DE-588)4179380-8 (DE-588)4113937-9 |
| title | Dual-loop gate drivers with analog and digital slope shaping |
| title_auth | Dual-loop gate drivers with analog and digital slope shaping |
| title_exact_search | Dual-loop gate drivers with analog and digital slope shaping |
| title_exact_search_txtP | Dual-loop gate drivers with analog and digital slope shaping |
| title_full | Dual-loop gate drivers with analog and digital slope shaping von Johannes Matthias Gröger, M. Sc. |
| title_fullStr | Dual-loop gate drivers with analog and digital slope shaping von Johannes Matthias Gröger, M. Sc. |
| title_full_unstemmed | Dual-loop gate drivers with analog and digital slope shaping von Johannes Matthias Gröger, M. Sc. |
| title_short | Dual-loop gate drivers with analog and digital slope shaping |
| title_sort | dual loop gate drivers with analog and digital slope shaping |
| topic | Mehrfachregelung (DE-588)7649005-1 gnd Schaltregler (DE-588)4179380-8 gnd |
| topic_facet | Mehrfachregelung Schaltregler Hochschulschrift |
| url | https://d-nb.info/1206348143/04 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=032597438&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT grogerjohannesmatthias dualloopgatedriverswithanaloganddigitalslopeshaping |
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