A primer on memory persistency:
This book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
San Rafael
Morgan & Claypool Publishers
2022
|
| Schriftenreihe: | Synthesis lectures on computer architecture
58 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Zusammenfassung: | This book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane DC persistent memories, are commercially available today. Unlike traditional storage devices, PMs can be accessed over a byte-addressable load-store interface with access latency that is comparable to DRAM. Unfortunately, existing hardware and software systems are ill-equipped to fully avail the potential of these byte-addressable memory technologies as they have been designed to access traditional storage media over a block-based interface.- Several mechanisms have been explored in the research literature over the past decade to design hardware and software systems that provide high-performance access to PMs.Because PMs are durable, they can retain data across failures, such as power failures and program crashes. Upon a failure, recovery mechanisms may inspect PM data, reconstruct state and resume program execution. Correct recovery of data requires that operations to the PM are properly ordered during normal program execution. Memory persistency models define the order in which memory operations are performed at the PM. Much like memory consistency models, memory persistency models may be relaxed to improve application performance. Several proposals have emerged recently to design memory persistency models for hardware and software systems and for high-level programming languages.- These proposals differ in several key aspects; they relax PM ordering constraints, introduce varying programmability burden, and introduce differing granularity of failure atomicity for PM operations.This primer provides a detailed overview of the various classes of the memory persistency models, their implementations in hardware, programming languages and software systems proposed in the recent research literature, and the PM ordering techniques employed by modern processors. |
| Beschreibung: | Includes bibliographical references |
| Beschreibung: | xix, 95 Seiten Diagramme |
| ISBN: | 9781636393063 9781636393049 |
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| 245 | 1 | 0 | |a A primer on memory persistency |c Vaibhav Gogte (University of Michigan), Aasheesh Kolli (Pennsylvania State University, Thomas F. Wenisch (University of Michigan) |
| 264 | 1 | |a San Rafael |b Morgan & Claypool Publishers |c 2022 | |
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| 490 | 1 | |a Synthesis lectures on computer architecture |v 58 | |
| 500 | |a Includes bibliographical references | ||
| 505 | 8 | |a - Preface; - Acknowledgments; - Persistent Memories; - Data Persistence; - Memory Persistency Models; - Hardware Mechanisms for Atomic Durability; - Programming Persistent Memory Systems; - Conclusion; - Bibliography; - Authors' Biographies; | |
| 520 | 3 | |a This book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane DC persistent memories, are commercially available today. Unlike traditional storage devices, PMs can be accessed over a byte-addressable load-store interface with access latency that is comparable to DRAM. Unfortunately, existing hardware and software systems are ill-equipped to fully avail the potential of these byte-addressable memory technologies as they have been designed to access traditional storage media over a block-based interface.- | |
| 520 | 3 | |a Several mechanisms have been explored in the research literature over the past decade to design hardware and software systems that provide high-performance access to PMs.Because PMs are durable, they can retain data across failures, such as power failures and program crashes. Upon a failure, recovery mechanisms may inspect PM data, reconstruct state and resume program execution. Correct recovery of data requires that operations to the PM are properly ordered during normal program execution. Memory persistency models define the order in which memory operations are performed at the PM. Much like memory consistency models, memory persistency models may be relaxed to improve application performance. Several proposals have emerged recently to design memory persistency models for hardware and software systems and for high-level programming languages.- | |
| 520 | 3 | |a These proposals differ in several key aspects; they relax PM ordering constraints, introduce varying programmability burden, and introduce differing granularity of failure atomicity for PM operations.This primer provides a detailed overview of the various classes of the memory persistency models, their implementations in hardware, programming languages and software systems proposed in the recent research literature, and the PM ordering techniques employed by modern processors. | |
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| 830 | 0 | |a Synthesis lectures on computer architecture |v 58 |w (DE-604)BV023068349 |9 58 | |
| 856 | 4 | 2 | |m Digitalisierung UB Passau - ADAM Catalogue Enrichment |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=033891758&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
Datensatz im Suchindex
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| adam_text |
xi Contents Preface . xv Acknowledgments . xix 1 2 3 Persistent Memories. 1 1.1 Introduction. 1 1.2 Persistent Memory Technologies.2 1.3 Intel Optane DC Persistent Memory. 4 1.3.1 Performance of Optane DC Persistent Memory.4 1.3.2 Modeling Persistent Memory Systems. 5 1.4 System Configurations. 6 1.4.1 Traditional Storage Systems. 6 1.4.2 Persistent Memory System. 8 1.4.3 Persistent Memory Support in ExistingFile Systems. 9 1.4.4 Persistent Memory File Systems . 9 1.4.5 Direct Access to Persistent Memories. 10 Data
Persistence. 13 2.1 Ensuring Data Durability. 13 2.1.1 Persistence at CPU Caches. 14 2.1.2 Persistence at PM Controller. 15 2.1.3 Persistence at Persistent Memory Device.16 2.1.4 A RM v8.2 ISA Extensions. 17 2.2 Ordering Memory Operations to PM. 17 2.2.1 Why is Ordering Required?. 17 2.2.2Sources of PM Operation Reordering. 18 2.2.3 Applying Correct Memory Order to PM . 20 Memory Persistency Models.21 3.1 Persistency Models. 21 3.2 Recovery Observer. 22 3.3 Strict Persistency . 23
3.3.1 3.3.2 3.3.3 Buffered Strict Persistency Model. Formalizing the Strict Persistency Model. Persist Ordering Examples. 3.4 Hardware Implementations of Strict Persistency. 3.4.1 Naive Implementation . 3.4.2 Bulk Persistence . 3.4.3 Delegated Persistence. 3.5 Drawbacks or Strict Persistency. 3.6 Epoch 3.6.1 3.6.2 3.6.3 3.6.4 3.7 Hardware implementations of Epoch Persistency. 3.7.1 Naive Implementation. 3.7.2 Buffered Epoch Persistency in Hardware. 3.7.3 Offline Conflict Resolution . 3.7.4 Separate Ordering and Durability Barriers. 3.8 Drawbacks of Epoch Persistency. 3.9 Strand 3.9.1 3.9.2 3.9.3 3.10 Hardware Implementations of Strand Persistency. Persistency
Model. Strong Persist Atomicity. Buffered Epoch Persistency Model . Formalizing the Epoch Persistency Model. . Persist Ordering Examples. Persistency Model. . . Strong Persist Atomicity. Formalizing rhe Strand Persistency Model . Persist Ordering Examples. Hardware Mechanisms for Atomic Durability. . 4.1 Failure 4.1.1 4.1.2 4.1.3 4.2 Failure֊Atomic Mechanisms. 4.3 Hardware Undo Logging. 4.3.1 Naive Implementation . 4.3.2 Optimized Undo Logging. 4.3.3 Software-Assisted Hardware Logging. , 4.4 Hardware Redo Logging. 4.4.1
Optimized Redo Logging. Atomicity'. Write-Ahead Logging. Log Structuring . Shadow Paging.
xiii 4.4.2 4.5 5 (į Durable J birdware Transactions. 62 Hardware Checkpointing Mechanisms. 63 4.5.1 Coarse-Grained Checkpointing. 63 4.3.2 Checkpointing on Power Failure. 64 Programming Persistent Memory Systems . 65 5.1 File Systems. 65 5.1.1 K\t4 DAX. 65 5.1.2 NOVA lole System. 67 5.1.3 SplitFS. 68 5.1.4 Strata. 69 5.2 Programming PM Systems. 70 5.2.1 Transactional Failure Atomicity. 70 5.2.2 Intel’s PMDK libraries. 71 5.2.3 Deferred Commit Transactions. 72 5.2.4 l'ailure Atomicity for
Outer-Critical Section . 72 5.2.5 l'ailure Atomicity for Synchronization Free Region. 73 5.3 lesting PM Applications.75 Conclusion . 77 Bibliography. 79 Authors’ Biographies. 95 |
| adam_txt |
xi Contents Preface . xv Acknowledgments . xix 1 2 3 Persistent Memories. 1 1.1 Introduction. 1 1.2 Persistent Memory Technologies.2 1.3 Intel Optane DC Persistent Memory. 4 1.3.1 Performance of Optane DC Persistent Memory.4 1.3.2 Modeling Persistent Memory Systems. 5 1.4 System Configurations. 6 1.4.1 Traditional Storage Systems. 6 1.4.2 Persistent Memory System. 8 1.4.3 Persistent Memory Support in ExistingFile Systems. 9 1.4.4 Persistent Memory File Systems . 9 1.4.5 Direct Access to Persistent Memories. 10 Data
Persistence. 13 2.1 Ensuring Data Durability. 13 2.1.1 Persistence at CPU Caches. 14 2.1.2 Persistence at PM Controller. 15 2.1.3 Persistence at Persistent Memory Device.16 2.1.4 A RM v8.2 ISA Extensions. 17 2.2 Ordering Memory Operations to PM. 17 2.2.1 Why is Ordering Required?. 17 2.2.2Sources of PM Operation Reordering. 18 2.2.3 Applying Correct Memory Order to PM . 20 Memory Persistency Models.21 3.1 Persistency Models. 21 3.2 Recovery Observer. 22 3.3 Strict Persistency . 23
3.3.1 3.3.2 3.3.3 Buffered Strict Persistency Model. Formalizing the Strict Persistency Model. Persist Ordering Examples. 3.4 Hardware Implementations of Strict Persistency. 3.4.1 Naive Implementation . 3.4.2 Bulk Persistence . 3.4.3 Delegated Persistence. 3.5 Drawbacks or Strict Persistency. 3.6 Epoch 3.6.1 3.6.2 3.6.3 3.6.4 3.7 Hardware implementations of Epoch Persistency. 3.7.1 Naive Implementation. 3.7.2 Buffered Epoch Persistency in Hardware. 3.7.3 Offline Conflict Resolution . 3.7.4 Separate Ordering and Durability Barriers. 3.8 Drawbacks of Epoch Persistency. 3.9 Strand 3.9.1 3.9.2 3.9.3 3.10 Hardware Implementations of Strand Persistency. Persistency
Model. Strong Persist Atomicity. Buffered Epoch Persistency Model . Formalizing the Epoch Persistency Model. . Persist Ordering Examples. Persistency Model. . . Strong Persist Atomicity. Formalizing rhe Strand Persistency Model . Persist Ordering Examples. Hardware Mechanisms for Atomic Durability. . 4.1 Failure 4.1.1 4.1.2 4.1.3 4.2 Failure֊Atomic Mechanisms. 4.3 Hardware Undo Logging. 4.3.1 Naive Implementation . 4.3.2 Optimized Undo Logging. 4.3.3 Software-Assisted Hardware Logging. , 4.4 Hardware Redo Logging. 4.4.1
Optimized Redo Logging. Atomicity'. Write-Ahead Logging. Log Structuring . Shadow Paging.
xiii 4.4.2 4.5 5 (į Durable J birdware Transactions. 62 Hardware Checkpointing Mechanisms. 63 4.5.1 Coarse-Grained Checkpointing. 63 4.3.2 Checkpointing on Power Failure. 64 Programming Persistent Memory Systems . 65 5.1 File Systems. 65 5.1.1 K\t4 DAX. 65 5.1.2 NOVA lole System. 67 5.1.3 SplitFS. 68 5.1.4 Strata. 69 5.2 Programming PM Systems. 70 5.2.1 Transactional Failure Atomicity. 70 5.2.2 Intel’s PMDK libraries. 71 5.2.3 Deferred Commit Transactions. 72 5.2.4 l'ailure Atomicity for
Outer-Critical Section . 72 5.2.5 l'ailure Atomicity for Synchronization Free Region. 73 5.3 lesting PM Applications.75 Conclusion . 77 Bibliography. 79 Authors’ Biographies. 95 |
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| author | Gogte, Vaibhav ca. 20./21. Jh Kolli, Aasheesh ca. 20./21. Jh Wenisch, Thomas F. ca. 20./21. Jh |
| author_GND | (DE-588)1283693658 (DE-588)1283693925 (DE-588)1283694212 |
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| contents | - Preface; - Acknowledgments; - Persistent Memories; - Data Persistence; - Memory Persistency Models; - Hardware Mechanisms for Atomic Durability; - Programming Persistent Memory Systems; - Conclusion; - Bibliography; - Authors' Biographies; |
| ctrlnum | (OCoLC)1373390225 (DE-599)KXP1796257893 |
| dewey-raw | a004.53c23 |
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| discipline | Informatik |
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| id | DE-604.BV048514818 |
| illustrated | Not Illustrated |
| index_date | 2024-07-03T20:48:47Z |
| indexdate | 2024-07-20T06:37:30Z |
| institution | BVB |
| isbn | 9781636393063 9781636393049 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-033891758 |
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| physical | xix, 95 Seiten Diagramme |
| publishDate | 2022 |
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| series | Synthesis lectures on computer architecture |
| series2 | Synthesis lectures on computer architecture |
| spelling | Gogte, Vaibhav ca. 20./21. Jh. Verfasser (DE-588)1283693658 aut A primer on memory persistency Vaibhav Gogte (University of Michigan), Aasheesh Kolli (Pennsylvania State University, Thomas F. Wenisch (University of Michigan) San Rafael Morgan & Claypool Publishers 2022 xix, 95 Seiten Diagramme txt rdacontent n rdamedia nc rdacarrier Synthesis lectures on computer architecture 58 Includes bibliographical references - Preface; - Acknowledgments; - Persistent Memories; - Data Persistence; - Memory Persistency Models; - Hardware Mechanisms for Atomic Durability; - Programming Persistent Memory Systems; - Conclusion; - Bibliography; - Authors' Biographies; This book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane DC persistent memories, are commercially available today. Unlike traditional storage devices, PMs can be accessed over a byte-addressable load-store interface with access latency that is comparable to DRAM. Unfortunately, existing hardware and software systems are ill-equipped to fully avail the potential of these byte-addressable memory technologies as they have been designed to access traditional storage media over a block-based interface.- Several mechanisms have been explored in the research literature over the past decade to design hardware and software systems that provide high-performance access to PMs.Because PMs are durable, they can retain data across failures, such as power failures and program crashes. Upon a failure, recovery mechanisms may inspect PM data, reconstruct state and resume program execution. Correct recovery of data requires that operations to the PM are properly ordered during normal program execution. Memory persistency models define the order in which memory operations are performed at the PM. Much like memory consistency models, memory persistency models may be relaxed to improve application performance. Several proposals have emerged recently to design memory persistency models for hardware and software systems and for high-level programming languages.- These proposals differ in several key aspects; they relax PM ordering constraints, introduce varying programmability burden, and introduce differing granularity of failure atomicity for PM operations.This primer provides a detailed overview of the various classes of the memory persistency models, their implementations in hardware, programming languages and software systems proposed in the recent research literature, and the PM ordering techniques employed by modern processors. Computer Storage Devices Computer storage devices fast Computer storage devices Speicher Informatik (DE-588)4077653-0 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Persistenz Informatik (DE-588)4247899-6 gnd rswk-swf Rechnerarchitektur EDV & Informatik Allgemein Ordinateurs / Mémoires Information technology: general issues Computer science Persistenz Informatik (DE-588)4247899-6 s Speicher Informatik (DE-588)4077653-0 s Computerarchitektur (DE-588)4048717-9 s DE-604 Kolli, Aasheesh ca. 20./21. Jh. Verfasser (DE-588)1283693925 aut Wenisch, Thomas F. ca. 20./21. Jh. Verfasser (DE-588)1283694212 aut Erscheint auch als Online-Ausgabe, pdf 9781636393056 Synthesis lectures on computer architecture 58 (DE-604)BV023068349 58 Digitalisierung UB Passau - ADAM Catalogue Enrichment application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=033891758&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Gogte, Vaibhav ca. 20./21. Jh Kolli, Aasheesh ca. 20./21. Jh Wenisch, Thomas F. ca. 20./21. Jh A primer on memory persistency Synthesis lectures on computer architecture - Preface; - Acknowledgments; - Persistent Memories; - Data Persistence; - Memory Persistency Models; - Hardware Mechanisms for Atomic Durability; - Programming Persistent Memory Systems; - Conclusion; - Bibliography; - Authors' Biographies; Computer Storage Devices Computer storage devices fast Computer storage devices Speicher Informatik (DE-588)4077653-0 gnd Computerarchitektur (DE-588)4048717-9 gnd Persistenz Informatik (DE-588)4247899-6 gnd |
| subject_GND | (DE-588)4077653-0 (DE-588)4048717-9 (DE-588)4247899-6 |
| title | A primer on memory persistency |
| title_auth | A primer on memory persistency |
| title_exact_search | A primer on memory persistency |
| title_exact_search_txtP | A primer on memory persistency |
| title_full | A primer on memory persistency Vaibhav Gogte (University of Michigan), Aasheesh Kolli (Pennsylvania State University, Thomas F. Wenisch (University of Michigan) |
| title_fullStr | A primer on memory persistency Vaibhav Gogte (University of Michigan), Aasheesh Kolli (Pennsylvania State University, Thomas F. Wenisch (University of Michigan) |
| title_full_unstemmed | A primer on memory persistency Vaibhav Gogte (University of Michigan), Aasheesh Kolli (Pennsylvania State University, Thomas F. Wenisch (University of Michigan) |
| title_short | A primer on memory persistency |
| title_sort | a primer on memory persistency |
| topic | Computer Storage Devices Computer storage devices fast Computer storage devices Speicher Informatik (DE-588)4077653-0 gnd Computerarchitektur (DE-588)4048717-9 gnd Persistenz Informatik (DE-588)4247899-6 gnd |
| topic_facet | Computer Storage Devices Computer storage devices Speicher Informatik Computerarchitektur Persistenz Informatik |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=033891758&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV023068349 |
| work_keys_str_mv | AT gogtevaibhav aprimeronmemorypersistency AT kolliaasheesh aprimeronmemorypersistency AT wenischthomasf aprimeronmemorypersistency |