Parasitic-Aware Optimization of CMOS RF Circuits:
In the arena of Parasitic-Aware Design of CMOS RF Circuits, efforts are aimed at the realization of true single-chip radios with few, if any, off-chip components. Ironically, the on-chip passive components required for RF integration pose miore serious challenges to SOC integration than the active C...
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| Main Authors: | , , |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Boston, MA
Springer US
2003
|
| Subjects: | |
| Online Access: | FHI01 BTU01 Volltext |
| Summary: | In the arena of Parasitic-Aware Design of CMOS RF Circuits, efforts are aimed at the realization of true single-chip radios with few, if any, off-chip components. Ironically, the on-chip passive components required for RF integration pose miore serious challenges to SOC integration than the active CMOS and BJT devices. This is not surprising since modern digital IC designs are dominated as much, or more, by interconnectg characteristics than by active device properties. In any event, the co-integration of active and passive devices in RFIC design represents a serious design problem and an even more daunting manufacturing challenge. If conventional mixed-signal design techniques are employed, parasitics associated with passive elements (resistors, capacitors, inductors, transformers, pads, etc.) and the package effectively de-tune RF circuits rendering them sub-optimal or virtually useless. Hence, dealing with parasitics in an effective way as part of the design process is an essential emerging methodology in modern SOC design. The parasitic-aware RF circuit synthesis techinques described in this book effectively address this critical problem |
| Physical Description: | 1 Online-Ressource (XVII, 162 p. 28 illus) |
| ISBN: | 9780306481291 |
| DOI: | 10.1007/b101853 |
Staff View
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV045148545 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 180827s2003 |||| o||u| ||||||eng d | ||
| 020 | |a 9780306481291 |9 978-0-306-48129-1 | ||
| 024 | 7 | |a 10.1007/b101853 |2 doi | |
| 035 | |a (ZDB-2-ENG)978-0-306-48129-1 | ||
| 035 | |a (OCoLC)1050952476 | ||
| 035 | |a (DE-599)BVBBV045148545 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-573 |a DE-634 | ||
| 082 | 0 | |a 621.3815 |2 23 | |
| 100 | 1 | |a Allstot, David J. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Parasitic-Aware Optimization of CMOS RF Circuits |c by David J. Allstot, Kiyong Choi, Jinho Park |
| 264 | 1 | |a Boston, MA |b Springer US |c 2003 | |
| 300 | |a 1 Online-Ressource (XVII, 162 p. 28 illus) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 520 | |a In the arena of Parasitic-Aware Design of CMOS RF Circuits, efforts are aimed at the realization of true single-chip radios with few, if any, off-chip components. Ironically, the on-chip passive components required for RF integration pose miore serious challenges to SOC integration than the active CMOS and BJT devices. This is not surprising since modern digital IC designs are dominated as much, or more, by interconnectg characteristics than by active device properties. In any event, the co-integration of active and passive devices in RFIC design represents a serious design problem and an even more daunting manufacturing challenge. If conventional mixed-signal design techniques are employed, parasitics associated with passive elements (resistors, capacitors, inductors, transformers, pads, etc.) and the package effectively de-tune RF circuits rendering them sub-optimal or virtually useless. Hence, dealing with parasitics in an effective way as part of the design process is an essential emerging methodology in modern SOC design. The parasitic-aware RF circuit synthesis techinques described in this book effectively address this critical problem | ||
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Circuits and Systems | |
| 650 | 4 | |a Electrical Engineering | |
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Electrical engineering | |
| 650 | 4 | |a Electronic circuits | |
| 700 | 1 | |a Choi, Kiyong |4 aut | |
| 700 | 1 | |a Park, Jinho |4 aut | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9781402073991 |
| 856 | 4 | 0 | |u https://doi.org/10.1007/b101853 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
| 912 | |a ZDB-2-ENG | ||
| 940 | 1 | |q ZDB-2-ENG_2000/2004 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030538244 | ||
| 966 | e | |u https://doi.org/10.1007/b101853 |l FHI01 |p ZDB-2-ENG |q ZDB-2-ENG_2000/2004 |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/b101853 |l BTU01 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext | |
Record in the Search Index
| _version_ | 1804178818660827136 |
|---|---|
| any_adam_object | |
| author | Allstot, David J. Choi, Kiyong Park, Jinho |
| author_facet | Allstot, David J. Choi, Kiyong Park, Jinho |
| author_role | aut aut aut |
| author_sort | Allstot, David J. |
| author_variant | d j a dj dja k c kc j p jp |
| building | Verbundindex |
| bvnumber | BV045148545 |
| collection | ZDB-2-ENG |
| ctrlnum | (ZDB-2-ENG)978-0-306-48129-1 (OCoLC)1050952476 (DE-599)BVBBV045148545 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/b101853 |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02787nmm a2200469zc 4500</leader><controlfield tag="001">BV045148545</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180827s2003 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780306481291</subfield><subfield code="9">978-0-306-48129-1</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/b101853</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-0-306-48129-1</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1050952476</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045148545</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-573</subfield><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Allstot, David J.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Parasitic-Aware Optimization of CMOS RF Circuits</subfield><subfield code="c">by David J. Allstot, Kiyong Choi, Jinho Park</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">2003</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XVII, 162 p. 28 illus)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">In the arena of Parasitic-Aware Design of CMOS RF Circuits, efforts are aimed at the realization of true single-chip radios with few, if any, off-chip components. Ironically, the on-chip passive components required for RF integration pose miore serious challenges to SOC integration than the active CMOS and BJT devices. This is not surprising since modern digital IC designs are dominated as much, or more, by interconnectg characteristics than by active device properties. In any event, the co-integration of active and passive devices in RFIC design represents a serious design problem and an even more daunting manufacturing challenge. If conventional mixed-signal design techniques are employed, parasitics associated with passive elements (resistors, capacitors, inductors, transformers, pads, etc.) and the package effectively de-tune RF circuits rendering them sub-optimal or virtually useless. Hence, dealing with parasitics in an effective way as part of the design process is an essential emerging methodology in modern SOC design. The parasitic-aware RF circuit synthesis techinques described in this book effectively address this critical problem</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Choi, Kiyong</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Park, Jinho</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9781402073991</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/b101853</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_2000/2004</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030538244</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/b101853</subfield><subfield code="l">FHI01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_2000/2004</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/b101853</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV045148545 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:01Z |
| institution | BVB |
| isbn | 9780306481291 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030538244 |
| oclc_num | 1050952476 |
| open_access_boolean | |
| owner | DE-573 DE-634 |
| owner_facet | DE-573 DE-634 |
| physical | 1 Online-Ressource (XVII, 162 p. 28 illus) |
| psigel | ZDB-2-ENG ZDB-2-ENG_2000/2004 ZDB-2-ENG ZDB-2-ENG_2000/2004 ZDB-2-ENG ZDB-2-ENG_Archiv |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Springer US |
| record_format | marc |
| spelling | Allstot, David J. Verfasser aut Parasitic-Aware Optimization of CMOS RF Circuits by David J. Allstot, Kiyong Choi, Jinho Park Boston, MA Springer US 2003 1 Online-Ressource (XVII, 162 p. 28 illus) txt rdacontent c rdamedia cr rdacarrier In the arena of Parasitic-Aware Design of CMOS RF Circuits, efforts are aimed at the realization of true single-chip radios with few, if any, off-chip components. Ironically, the on-chip passive components required for RF integration pose miore serious challenges to SOC integration than the active CMOS and BJT devices. This is not surprising since modern digital IC designs are dominated as much, or more, by interconnectg characteristics than by active device properties. In any event, the co-integration of active and passive devices in RFIC design represents a serious design problem and an even more daunting manufacturing challenge. If conventional mixed-signal design techniques are employed, parasitics associated with passive elements (resistors, capacitors, inductors, transformers, pads, etc.) and the package effectively de-tune RF circuits rendering them sub-optimal or virtually useless. Hence, dealing with parasitics in an effective way as part of the design process is an essential emerging methodology in modern SOC design. The parasitic-aware RF circuit synthesis techinques described in this book effectively address this critical problem Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Choi, Kiyong aut Park, Jinho aut Erscheint auch als Druck-Ausgabe 9781402073991 https://doi.org/10.1007/b101853 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Allstot, David J. Choi, Kiyong Park, Jinho Parasitic-Aware Optimization of CMOS RF Circuits Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits |
| title | Parasitic-Aware Optimization of CMOS RF Circuits |
| title_auth | Parasitic-Aware Optimization of CMOS RF Circuits |
| title_exact_search | Parasitic-Aware Optimization of CMOS RF Circuits |
| title_full | Parasitic-Aware Optimization of CMOS RF Circuits by David J. Allstot, Kiyong Choi, Jinho Park |
| title_fullStr | Parasitic-Aware Optimization of CMOS RF Circuits by David J. Allstot, Kiyong Choi, Jinho Park |
| title_full_unstemmed | Parasitic-Aware Optimization of CMOS RF Circuits by David J. Allstot, Kiyong Choi, Jinho Park |
| title_short | Parasitic-Aware Optimization of CMOS RF Circuits |
| title_sort | parasitic aware optimization of cmos rf circuits |
| topic | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits |
| url | https://doi.org/10.1007/b101853 |
| work_keys_str_mv | AT allstotdavidj parasiticawareoptimizationofcmosrfcircuits AT choikiyong parasiticawareoptimizationofcmosrfcircuits AT parkjinho parasiticawareoptimizationofcmosrfcircuits |