Formal Equivalence Checking and Design Debugging:
Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1998
|
| Schriftenreihe: | Frontiers in Electronic Testing
12 |
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: 'With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley |
| Beschreibung: | 1 Online-Ressource (XVIII, 229 p) |
| ISBN: | 9781461556930 |
| DOI: | 10.1007/978-1-4615-5693-0 |
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| 520 | |a Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: 'With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley | ||
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Datensatz im Suchindex
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| author | Huang, Shi-Yu Cheng, Kwang-Ting (Tim) |
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| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
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| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4615-5693-0 |
| format | Electronic eBook |
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| id | DE-604.BV045184823 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:54Z |
| institution | BVB |
| isbn | 9781461556930 |
| language | English |
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| publishDate | 1998 |
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| series2 | Frontiers in Electronic Testing |
| spelling | Huang, Shi-Yu Verfasser aut Formal Equivalence Checking and Design Debugging by Shi-Yu Huang, Kwang-Ting (Tim) Cheng Boston, MA Springer US 1998 1 Online-Ressource (XVIII, 229 p) txt rdacontent c rdamedia cr rdacarrier Frontiers in Electronic Testing 12 Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: 'With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley Engineering Circuits and Systems Computing Methodologies Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computers Computer-aided engineering Electrical engineering Electronic circuits Cheng, Kwang-Ting (Tim) aut Erscheint auch als Druck-Ausgabe 9781461376064 https://doi.org/10.1007/978-1-4615-5693-0 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Huang, Shi-Yu Cheng, Kwang-Ting (Tim) Formal Equivalence Checking and Design Debugging Engineering Circuits and Systems Computing Methodologies Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computers Computer-aided engineering Electrical engineering Electronic circuits |
| title | Formal Equivalence Checking and Design Debugging |
| title_auth | Formal Equivalence Checking and Design Debugging |
| title_exact_search | Formal Equivalence Checking and Design Debugging |
| title_full | Formal Equivalence Checking and Design Debugging by Shi-Yu Huang, Kwang-Ting (Tim) Cheng |
| title_fullStr | Formal Equivalence Checking and Design Debugging by Shi-Yu Huang, Kwang-Ting (Tim) Cheng |
| title_full_unstemmed | Formal Equivalence Checking and Design Debugging by Shi-Yu Huang, Kwang-Ting (Tim) Cheng |
| title_short | Formal Equivalence Checking and Design Debugging |
| title_sort | formal equivalence checking and design debugging |
| topic | Engineering Circuits and Systems Computing Methodologies Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computers Computer-aided engineering Electrical engineering Electronic circuits |
| topic_facet | Engineering Circuits and Systems Computing Methodologies Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computers Computer-aided engineering Electrical engineering Electronic circuits |
| url | https://doi.org/10.1007/978-1-4615-5693-0 |
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