Resource efficient LDPC decoders: from algorithms to hardware architectures
This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
London
Academic Press, an imprint of Elsevier
[2018]
|
| Schlagworte: | |
| Online-Zugang: | FLA01 FAW01 Volltext |
| Zusammenfassung: | This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. The reader will learn: Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementationHow to reduce computational complexity and power consumption using computer aided design techniquesAll aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs |
| Beschreibung: | Includes bibliographical references and index |
| Beschreibung: | 1 online resource color illustrations |
| ISBN: | 9780128112564 0128112565 |
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Datensatz im Suchindex
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| author | Chansetty, Vikram Arkalgud Aziz, Syed Mahfuzul |
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| dewey-full | 621.38932 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.38932 |
| dewey-search | 621.38932 |
| dewey-sort | 3621.38932 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | DE-604.BV045131767 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T08:09:35Z |
| institution | BVB |
| isbn | 9780128112564 0128112565 |
| language | English |
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| physical | 1 online resource color illustrations |
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| publishDate | 2018 |
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| publisher | Academic Press, an imprint of Elsevier |
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| spelling | Chansetty, Vikram Arkalgud Verfasser aut Resource efficient LDPC decoders from algorithms to hardware architectures Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz London Academic Press, an imprint of Elsevier [2018] © 2018 1 online resource color illustrations txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references and index This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. The reader will learn: Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementationHow to reduce computational complexity and power consumption using computer aided design techniquesAll aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs TECHNOLOGY & ENGINEERING / Mechanical bisacsh Decoders (Electronics) fast Digital communications fast Decoders (Electronics) Digital communications Aziz, Syed Mahfuzul aut Erscheint auch als Druck-Ausgabe 9780128112557 https://www.sciencedirect.com/science/book/9780128112557 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Chansetty, Vikram Arkalgud Aziz, Syed Mahfuzul Resource efficient LDPC decoders from algorithms to hardware architectures TECHNOLOGY & ENGINEERING / Mechanical bisacsh Decoders (Electronics) fast Digital communications fast Decoders (Electronics) Digital communications |
| title | Resource efficient LDPC decoders from algorithms to hardware architectures |
| title_auth | Resource efficient LDPC decoders from algorithms to hardware architectures |
| title_exact_search | Resource efficient LDPC decoders from algorithms to hardware architectures |
| title_full | Resource efficient LDPC decoders from algorithms to hardware architectures Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz |
| title_fullStr | Resource efficient LDPC decoders from algorithms to hardware architectures Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz |
| title_full_unstemmed | Resource efficient LDPC decoders from algorithms to hardware architectures Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz |
| title_short | Resource efficient LDPC decoders |
| title_sort | resource efficient ldpc decoders from algorithms to hardware architectures |
| title_sub | from algorithms to hardware architectures |
| topic | TECHNOLOGY & ENGINEERING / Mechanical bisacsh Decoders (Electronics) fast Digital communications fast Decoders (Electronics) Digital communications |
| topic_facet | TECHNOLOGY & ENGINEERING / Mechanical Decoders (Electronics) Digital communications |
| url | https://www.sciencedirect.com/science/book/9780128112557 |
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