Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method
Standardization of hardware description languages and the availability of synthesis tools has brought about a remarkable increase in the productivity of hardware designers. Yet design verification methods and tools lag behind and have difficulty in dealing with the increasing design complexity. This...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1998
|
| Schlagworte: | |
| Online-Zugang: | BTU01 URL des Erstveröffentlichers |
| Zusammenfassung: | Standardization of hardware description languages and the availability of synthesis tools has brought about a remarkable increase in the productivity of hardware designers. Yet design verification methods and tools lag behind and have difficulty in dealing with the increasing design complexity. This may get worse because more complex systems are now constructed by (re)using Intellectual Property blocks developed by third parties. To verify such designs, abstract models of the blocks and the system must be developed, with separate concerns, such as interface communication, functionality, and timing, that can be verified in an almost independent fashion. Standard Hardware Description Languages such as VHDL and Verilog are inspired by procedural 'imperative' programming languages in which function and timing are inherently intertwined in the statements of the language. Furthermore, they are not conceived to state the intent of the design in a simple declarative way that contains provisions for design choices, for stating assumptions on the environment, and for indicating uncertainty in system timing. Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method presents a description methodology that was inspired by Timing Diagrams and Process Algebras, the so-called Hierarchical Annotated Diagrams. It is suitable for specifying systems with complex interface behaviors that govern the global system behavior. A HADD specification can be converted into a behavioral real-time model in VHDL and used to verify the surrounding logic, such as interface transducers. Also, function can be conservatively abstracted away and the interactions between interconnected devices can be verified using Constraint Logic Programming based on Relational Interval Arithmetic. Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method is of interest to readers who are involved in defining methods and tools for system-level design specification and verification. The techniques for interface compatibility verification can be used by practicing designers, without any more sophisticated tool than a calculator |
| Beschreibung: | 1 Online-Ressource (XVI, 211 p) |
| ISBN: | 9781461556152 |
| DOI: | 10.1007/978-1-4615-5615-2 |
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| 520 | |a Standardization of hardware description languages and the availability of synthesis tools has brought about a remarkable increase in the productivity of hardware designers. Yet design verification methods and tools lag behind and have difficulty in dealing with the increasing design complexity. This may get worse because more complex systems are now constructed by (re)using Intellectual Property blocks developed by third parties. To verify such designs, abstract models of the blocks and the system must be developed, with separate concerns, such as interface communication, functionality, and timing, that can be verified in an almost independent fashion. Standard Hardware Description Languages such as VHDL and Verilog are inspired by procedural 'imperative' programming languages in which function and timing are inherently intertwined in the statements of the language. | ||
| 520 | |a Furthermore, they are not conceived to state the intent of the design in a simple declarative way that contains provisions for design choices, for stating assumptions on the environment, and for indicating uncertainty in system timing. Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method presents a description methodology that was inspired by Timing Diagrams and Process Algebras, the so-called Hierarchical Annotated Diagrams. It is suitable for specifying systems with complex interface behaviors that govern the global system behavior. A HADD specification can be converted into a behavioral real-time model in VHDL and used to verify the surrounding logic, such as interface transducers. Also, function can be conservatively abstracted away and the interactions between interconnected devices can be verified using Constraint Logic Programming based on Relational Interval Arithmetic. | ||
| 520 | |a Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method is of interest to readers who are involved in defining methods and tools for system-level design specification and verification. The techniques for interface compatibility verification can be used by practicing designers, without any more sophisticated tool than a calculator | ||
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| 700 | 1 | |a Girodias, P. |4 aut | |
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| spelling | Cerny, E. Verfasser aut Hierarchical Annotated Action Diagrams An Interface-Oriented Specification and Verification Method by E. Cerny, B. Berkane, P. Girodias, K. Khordoc Boston, MA Springer US 1998 1 Online-Ressource (XVI, 211 p) txt rdacontent c rdamedia cr rdacarrier Standardization of hardware description languages and the availability of synthesis tools has brought about a remarkable increase in the productivity of hardware designers. Yet design verification methods and tools lag behind and have difficulty in dealing with the increasing design complexity. This may get worse because more complex systems are now constructed by (re)using Intellectual Property blocks developed by third parties. To verify such designs, abstract models of the blocks and the system must be developed, with separate concerns, such as interface communication, functionality, and timing, that can be verified in an almost independent fashion. Standard Hardware Description Languages such as VHDL and Verilog are inspired by procedural 'imperative' programming languages in which function and timing are inherently intertwined in the statements of the language. Furthermore, they are not conceived to state the intent of the design in a simple declarative way that contains provisions for design choices, for stating assumptions on the environment, and for indicating uncertainty in system timing. Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method presents a description methodology that was inspired by Timing Diagrams and Process Algebras, the so-called Hierarchical Annotated Diagrams. It is suitable for specifying systems with complex interface behaviors that govern the global system behavior. A HADD specification can be converted into a behavioral real-time model in VHDL and used to verify the surrounding logic, such as interface transducers. Also, function can be conservatively abstracted away and the interactions between interconnected devices can be verified using Constraint Logic Programming based on Relational Interval Arithmetic. Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method is of interest to readers who are involved in defining methods and tools for system-level design specification and verification. The techniques for interface compatibility verification can be used by practicing designers, without any more sophisticated tool than a calculator Engineering Circuits and Systems Computing Methodologies Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computers Computer-aided engineering Electrical engineering Electronic circuits Berkane, B. aut Girodias, P. aut Khordoc, K. aut Erscheint auch als Druck-Ausgabe 9781461375692 https://doi.org/10.1007/978-1-4615-5615-2 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Cerny, E. Berkane, B. Girodias, P. Khordoc, K. Hierarchical Annotated Action Diagrams An Interface-Oriented Specification and Verification Method Engineering Circuits and Systems Computing Methodologies Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computers Computer-aided engineering Electrical engineering Electronic circuits |
| title | Hierarchical Annotated Action Diagrams An Interface-Oriented Specification and Verification Method |
| title_auth | Hierarchical Annotated Action Diagrams An Interface-Oriented Specification and Verification Method |
| title_exact_search | Hierarchical Annotated Action Diagrams An Interface-Oriented Specification and Verification Method |
| title_full | Hierarchical Annotated Action Diagrams An Interface-Oriented Specification and Verification Method by E. Cerny, B. Berkane, P. Girodias, K. Khordoc |
| title_fullStr | Hierarchical Annotated Action Diagrams An Interface-Oriented Specification and Verification Method by E. Cerny, B. Berkane, P. Girodias, K. Khordoc |
| title_full_unstemmed | Hierarchical Annotated Action Diagrams An Interface-Oriented Specification and Verification Method by E. Cerny, B. Berkane, P. Girodias, K. Khordoc |
| title_short | Hierarchical Annotated Action Diagrams |
| title_sort | hierarchical annotated action diagrams an interface oriented specification and verification method |
| title_sub | An Interface-Oriented Specification and Verification Method |
| topic | Engineering Circuits and Systems Computing Methodologies Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computers Computer-aided engineering Electrical engineering Electronic circuits |
| topic_facet | Engineering Circuits and Systems Computing Methodologies Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computers Computer-aided engineering Electrical engineering Electronic circuits |
| url | https://doi.org/10.1007/978-1-4615-5615-2 |
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