Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics von Khatri, Sunil P., Brayton, Robert K., Sangiovanni-Vincentelli, Alberto L.

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Synthesis of Finite State Machines Logic Optimization von Villa, Tiziano, Kam, Timothy, Brayton, Robert K., Sangiovanni-Vincentelli, Alberto

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Logic Synthesis for Field-Programmable Gate Arrays von Murgai, Rajeev, Brayton, Robert K., Sangiovanni-Vincentelli, Alberto

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Timed Boolean functions a unified formalism for exact timing analysis von Lam, William K., Brayton, Robert K.

Integrating Functional and Temporal Domains in Logic Design The False Path Problem and Its Implications von McGeer, Patrick C., Brayton, Robert K.

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Synthesis of finite state machines functional optimization von Kam, Timothy, Villa, Tiziano, Brayton, Robert K.

Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design von Mo, Fan, Brayton, Robert K.

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Timed Boolean Functions A Unified Formalism for Exact Timing Analysis von Lam, William K. C., Brayton, Robert K.

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Integrating functional and temporal domains in logic design the false path problem and its implications von MacGeer, Patrick C., Brayton, Robert K.

Multi-level logic synthesis von Brayton, Robert K.

Logic Minimization Algorithms for VLSI Synthesis von Brayton, Robert K., Hachtel, Gary D., McMullen, Curtis T., Sangiovanni-Vincentelli, Alberto L.

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Sensitivity and optimization von Brayton, Robert K., Spence, Robert

Sensitivity and optimization von Brayton, Robert K., Spence, Robert

Cross talk noise immune VLSI design using regular layout fabrics von Khatri, Sunil P., Brayton, Robert K., Sangiovanni-Vincentelli, Alberto L.

Logic synthesis for field programmable gate arrays von Murgai, Rajeev, Brayton, Robert K., Sangiovanni-Vincentelli, Alberto

Logic Minimization Algorithms for VLSI synthesis

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