Verfügbarkeit: Synthesis of arithmetic circuits

Synthesis of arithmetic circuits: FPGA, ASIC and embedded systems

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Deschamps, Jean-Pierre (VerfasserIn), Bioul, Géry Jean Antoine (VerfasserIn), Sutter, Gustavo D. (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	Hoboken, N.J. Wiley 2006
Schlagworte:	Computer arithmetic and logic units Digital electronics Embedded computer systems Computerarithmetik Eingebettetes System Digitalelektronik
Online-Zugang:	Table of contents only Contributor biographical information Publisher description Inhaltsverzeichnis
Beschreibung:	XIX, 556 S. Ill., graph. Darst.
ISBN:	9780471687832 0471687839

Internformat

MARC


LEADER	00000nam a2200000zc 4500
001	BV023091889
003	DE-604
005	20100209
007	t
008	080122s2006 xxuad\|\| \|\|\|\| 00\|\|\| eng d
010			\|a 2005003237
020			\|a 9780471687832 \|9 978-0-471-68783-2
020			\|a 0471687839 \|c cloth \|9 0-471-68783-9
035			\|a (OCoLC)254061216
035			\|a (DE-599)BVBBV023091889
040			\|a DE-604 \|b ger \|e aacr
041	0		\|a eng
044			\|a xxu \|c US
049			\|a DE-706 \|a DE-573 \|a DE-83 \|a DE-Aug4 \|a DE-29T
050		0	\|a TK7895.A65
082	0		\|a 621.39/5
084			\|a ST 125 \|0 (DE-625)143586: \|2 rvk
084			\|a ST 150 \|0 (DE-625)143594: \|2 rvk
084			\|a ZN 4940 \|0 (DE-625)157423: \|2 rvk
100	1		\|a Deschamps, Jean-Pierre \|e Verfasser \|4 aut
245	1	0	\|a Synthesis of arithmetic circuits \|b FPGA, ASIC and embedded systems \|c Jean-Pierre Deschamps ; Géry Jean Antoine Bioul ; Gustavo D. Sutter
264		1	\|a Hoboken, N.J. \|b Wiley \|c 2006
300			\|a XIX, 556 S. \|b Ill., graph. Darst.
336			\|b txt \|2 rdacontent
337			\|b n \|2 rdamedia
338			\|b nc \|2 rdacarrier
650		4	\|a Computer arithmetic and logic units
650		4	\|a Digital electronics
650		4	\|a Embedded computer systems
650	0	7	\|a Computerarithmetik \|0 (DE-588)4135485-0 \|2 gnd \|9 rswk-swf
650	0	7	\|a Eingebettetes System \|0 (DE-588)4396978-1 \|2 gnd \|9 rswk-swf
650	0	7	\|a Digitalelektronik \|0 (DE-588)4260328-6 \|2 gnd \|9 rswk-swf
689	0	0	\|a Digitalelektronik \|0 (DE-588)4260328-6 \|D s
689	0	1	\|a Computerarithmetik \|0 (DE-588)4135485-0 \|D s
689	0	2	\|a Eingebettetes System \|0 (DE-588)4396978-1 \|D s
689	0		\|5 DE-604
700	1		\|a Bioul, Géry Jean Antoine \|e Verfasser \|4 aut
700	1		\|a Sutter, Gustavo D. \|e Verfasser \|4 aut
856	4		\|u http://www.loc.gov/catdir/toc/ecip057/2005003237.html \|3 Table of contents only
856	4		\|u http://www.loc.gov/catdir/enhancements/fy0621/2005003237-b.html \|3 Contributor biographical information
856	4		\|u http://www.loc.gov/catdir/enhancements/fy0621/2005003237-d.html \|3 Publisher description
856	4	2	\|m GBV Datenaustausch \|q application/pdf \|u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016294746&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA \|3 Inhaltsverzeichnis
999			\|a oai:aleph.bib-bvb.de:BVB01-016294746

Datensatz im Suchindex

_version_	1804137345188888576
adam_text	SYNTHESIS OF ARITHMETIC CIRCUITS FPGA, ASIC, AND EMBEDDED SYSTEMS JEAN-PIERRE DESCHAMPS UNIVERSITY ROVIRA I VIRGILI GERY JEAN ANTOINE BIOUL NATIONAL UNIVERSITY OF THE CENTER OF THE PROVINCE OF BUENOS AIRES GUSTAVO D. SUTTER UNIVERSITY AUTONOMA OF MADRID /X^WILEY- V^TYINTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION CONTENTS PREFACE XVII ABOUT THE AUTHORS XIX 1 INTRODUCTION 1 1.1 NUMBER REPRESENTATION, 1 1.2 ALGORITHMS, 2 1.3 HARDWARE PLATFORMS, 2 1.4 HARDWARE-SOFTWARE PARTITIONING, 3 1.5 SOFTWARE GENERATION, 3 .6 SYNTHT ;SIS, 3 .7 A FIRST EXAMPLE, 3 1.7.1 1.7.2 1.7.3 1.7.4 1.7.5 1.7.6 1.7.7 1.7.8 SPECIFICATION, 3 NUMBER REPRESENTATION, 6 ALGORITHMS, 6 HARDWARE PLATFORM, 8 HARDWARE-SOFTWARE PARTITIONIN; PROGRAM GENERATION, 9 SYNTHESIS, 10 PROTOTYPE, 12 1.8 BIBLIOGRAPHY, 14 VII JJJ CONTENTS 2 MATHEMATICAL BACKGROUND 15 2.1 NUMBER THEORY, 15 2.1.1 BASIC DEFINITIONS, 15 2.1.2 EUCLIDEAN ALGORITHMS, 17 2.1.3 CONGRUENCES, 19 2.2 ALGEBRA, 25 2.2.1 CROUPS, 25 2.2.2 RINGS, 27 2.2.3 FIELDS, 27 2.2.4 POLYNOMIAL RINGS, 27 2.2.5 CONGRUENCES OF POLYNOMIAL, 32 2.3 FUNCTION APPROXIMATION, 35 2.4 BIBLIOGRAPHY, 36 3 NUMBER REPRESENTATION 39 3.1 NATURAL NUMBERS, 39 3.1.1 WEIGHTED SYSTEMS, 39 3.1.2 RESIDUE NUMBER SYSTEM, 42 3.2 INTEGERS, 42 3.2.1 SIGN-MAGNITUDE REPRESENTATION, 42 3.2.2 EXCESS-E REPRESENTATION, 43 3.2.3 5 S COMPLEMENT REPRESENTATION, 44 3.2.4 BOOTH S ENCODING, 47 3.3 REAL NUMBERS, 51 3.4 BIBLIOGRAPHY, 54 4 ARITHMETIC OPERATIONS: ADDITION AND SUBTRACTION 55 4.1 ADDITION OF NATURAL NUMBERS, 55 4.1.1 BASIC ALGORITHM, 55 4.1.2 FASTER ALGORITHMS, 57 4.1.3 LONG-OPERAND ADDITION, 66 4.1.4 MULTIOPERAND ADDITION, 67 4.1.5 LONG-MULTIOPERAND ADDITION, 70 4.2 SUBTRACTION OF NATURAL NUMBERS, 71 4.3 INTEGERS, 71 4.3.1 SS S COMPLEMENT ADDITION, 71 4.3.2 SS S COMPLEMENT SIGN CHANGE, 72 4.3.3 SS S COMPLEMENT SUBTRACTION, 74 CONTENTS IX 4.3.4 B S COMPLEMENT OVERFLOW DETECTION, 74 4.3.5 EXCESS- ADDITION AND SUBTRACTION, 78 4.3.6 SIGN-MAGNITUDE ADDITION AND SUBTRACTION, 79 4.4 BIBLIOGRAPHY, 80 5 ARITHMETIC OPERATIONS: MULTIPLICATION 81 5.1 NATURAL NUMBERS MULTIPLICATION, 82 5.1.1 INTRODUCTION, 82 5.1.2 SHIFT AND ADD ALGORITHMS, 83 5.1.2.1 SHIFT AND ADD 1, 83 5.1.2.2 SHIFT AND ADD 2, 84 5.1.2.3 EXTENDED SHIFT AND ADD ALGORITHM: XY+C + D, 86 5.1.2.4 CELLULAR SHIFT AND ADD, 86 5.1.3 LONG-OPERAND ALGORITHM, 90 5.2 INTEGERS, 91 5.2.1 B S COMPLEMENT MULTIPLICATION, 91 5.2.1.1 MOD B +L B S COMPLEMENT MULTIPLICATION, 92 5.2.1.2 SIGNED SHIFT AND ADD, 93 5.2.1.3 POSTCORRECTION 5 S COMPLEMENT MULTIPLICATION, 93 5.2.2 POSTCORRECTION 2 S COMPLEMENT MULTIPLICATION, 96 5.2.3 BOOTH MULTIPLICATION FOR BINARY NUMBERS, 97 5.2.3.1 BOOTH-R ALGORITHMS, 97 5.2.3.2 PER GELOSIA SIGNED-DIGIT ALGORITHM, 98 5.2.4 BOOTH MULTIPLICATION FOR BASE-SS NUMBERS (BOOTH-R ALGORITHM IN BASE B), 102 5.3 SQUARING, 104 5.3.1 BASE-SS SQUARING, 104 5.3.1.1 CELLULAR CARRY-SAVE SQUARING ALGORITHM, 104 5.3.2 BASE-2 SQUARING, 106 5.4 BIBLIOGRAPHY, 107 6 ARITHMETIC OPERATIONS: DIVISION 109 6.1 NATURAL NUMBERS, 110 6.2 INTEGERS, 117 6.2.1 GENERAL ALGORITHM, 117 6.2.2 RESTORING DIVISION ALGORITHM, 121 6.2.3 BASE-2 NONRESTORING DIVISION ALGORITHM, 121 6.2.4 SRT RADIX-2 DIVISION, 126 6.2.5 SRT RADIX-2 DIVISION WITH STORED-CARRY ENCODING, 131 6.2.6 P-D DIAGRAM, 139 I CONTENTS 6.2.7 SRT-4 DIVISION, 142 6.2.8 BASE-SS NONRESTORING DIVISION ALGORITHM, 148 6.3 CONVERGENCE (FUNCTIONAL ITERATION) ALGORITHMS, 155 6.3.1 INTRODUCTION, 155 6.3.2 NEWTON-RAPHSON ITERATION TECHNIQUE, 155 6.3.3 MACLAURIN EXPANSIONGOLDSCHMIDT S ALGORITHM, 159 6.4 BIBLIOGRAPHY, 161 7 OTHER ARITHMETIC OPERATIONS 165 7.1 BASE CONVERSION, 165 7.2 RESIDUE NUMBER SYSTEM CONVERSION, 173 7.2.1 INTRODUCTION, 173 7.2.2 BASE-SS TO RNS CONVERSION, 173 7.2.3 RNS TO BASE-SS CONVERSION, 177 7.3 LOGARITHMIC, EXPONENTIAL, AND TRIGONOMETRIE FUNCTIONS, 180 7.3.1 TAYLOR-MACLAURIN SERIES, 181 7.3.2 POLYNOMIAL APPROXIMATION, 183 7.3.3 LOGARITHM AND EXPONENTIAL FUNCTIONS APPROXIMATION BY CONVERGENCE METHODS, 184 7.3.3.1 LOGARITHM FUNCTION APPROXIMATION BY MULTIPLICATIVE NORMALIZATION, 184 7.3.3.2 EXPONENTIAL FUNCTION APPROXIMATION BY ADDITIVE NORMALIZATION, 188 7.3.4 TRIGONOMETRIE FUNCTIONSCORDIC ALGORITHMS, 194 7.4 SQUARE ROOTING, 198 7.4.1 DIGIT RECURRENCE ALGORITHMBASE-SS INTEGERS, 198 7.4.2 RESTORING BINARY SHIFT-AND-SUBTRACT SQUARE ROOTING ALGORITHM, 202 7.4.3 NONRESTORING BINARY ADD-AND-SUBTRACT SQUARE ROOTING ALGORITHM, 204 7.4.4 CONVERGENCE METHODNEWTON-RAPHSON, 208 7.5 BIBLIOGRAPHY, 208 8 FINITE FIELD OPERATIONS 211 8.1 OPERATIONS IN Z** 211 8.1.1 ADDITION, 212 8.1.2 SUBTRACTION, 213 8.1.3 MULTIPLICATION, 213 8.1.3.1 MULTIPLY AND REDUCE, 214 8.1.3.2 MODIFIED SHIFT-AND-ADD ALGORITHM, 214 CONTENTS XI 8.1.3.3 MONTGOMERY MULTIPLICATION, 216 8.1.3.4 SPECIFIC RING, 220 8.1.4 EXPONENTIATION, 221 8.2 OPERATIONS IN GF(P), 222 8.3 OPERATIONS IN Z P X]/F(X), 224 8.3.1 ADDITION AND SUBTRACTION, 224 8.3.2 MULTIPLICATION, 225 8.4 OPERATIONS IN GF(P ), 228 8.5 BIBLIOGRAPHY, 236 APPENDIX 8.1 COMPUTATION OFF KI , 236 9 HARDWARE PLATFORMS 239 9.1 DESIGN METHODS FOR ELECTRONIC SYSTEMS, 239 9.1.1 BASIC BLOCKS OF INTEGRATED SYSTEMS, 240 9.1.2 RECURRING TOPICS IN ELECTRONIC DESIGN, 241 9.1.2.1 DESIGN CHALLENGE: OPTIMIZING DESIGN METRICS, 241 9.1.2.2 COST IN INTEGRATED CIRCUITS, 242 9.1.2.3 MOORE S LAW, 243 9.1.2.4 TIME-TO-MARKET, 243 9.1.2.5 PERFORMANCE METRIE, 244 9.1.2.6 THE POWER DIMENSION, 245 9.2 INSTRUCTION SET PROCESSORS, 245 9.2.1 MICROPROCESSORS, 247 9.2.2 MICROCONTROLLERS, 248 9.2.3 EMBEDDED PROCESSORS EVERYWHERE, 248 9.2.4 DIGITAL SIGNAL PROCESSORS, 249 9.2.5 APPLICATION-SPECIFIC INSTRUCTION SET PROCESSORS, 250 9.2.6 PROGRAMMING INSTRUCTION SET PROCESSORS, 251 9.3 ASIC DESIGNS, 252 9.3.1 FULL-CUSTOM ASIC, 252 9.3.2 SEMICUSTOM ASIC, 253 9.3.2.1 GATE-ARRAY ASIC, 253 9.3.2.2 STANDARD-CELL-BASED ASIC, 254 9.3.3 DESIGN FLOW IN ASIC, 255 9.4 PROGRAMMABLE LOGIC, 256 9.4.1 PROGRAMMABLE LOGIC DEVICES (PLDS), 256 9.4.2 FIELD PROGRAMMABLE GATE ARRAY (FPGA), 258 9.4.2.1 WHY FPGA? A SHORT HISTORICAL SURVEY, 258 9.4.2.2 BASIC FPGA CONCEPTS, 258 XII CONTENTS 9.4.3 XILINX* SPECIFICS, 260 9.4.3.1 CONFIGURABLE LOGIC BLOCKS (CLBS), 262 9.4.3.2 INPUT/OUTPUT BLOCKS (IOBS), 262 9.4.3.3 RAM BLOCKS, 262 9.4.3.4 PROGRAMMABLE ROUTING, 264 9.4.3.5 ARITHMETIC RESOURCES IN XILINX FPGAS, 264 9.4.4 FPGA GENERIC DESIGN FLOW, 264 9.5 HARDWARE DESCRIPTION LANGUAGES (HDLS), 267 9.5.1 TODAY S AND TOMORROW S HDLS, 267 9.6 FURTHER READINGS, 268 9.7 BIBLIOGRAPHY, 268 10 CIRCUIT SYNTHESIS: GENERAL PRINCIPLES 271 10.1 RESOURCES, 272 10.2 PRECEDENCE RELATION AND SCHEDULING, 277 10.3 PIPELINE, 281 10.4 SELF-TIMED CIRCUITS, 282 10.5 BIBLIOGRAPHY, 288 11 ADDERS AND SUBTRACTORS 289 11.1 NATURAL NUMBERS, 289 11.1.1 BASIC ADDER (RIPPLE-CARRY ADDER), 289 11.1.2 CARRY-CHAIN ADDER, 292 11.1.3 CARRY-SKIP ADDER, 294 11.1.4 OPTIMIZATION OF CARRY-SKIP ADDERS, 298 11.1.5 BASE-SS V ADDER, 301 11.1.6 CARRY-SELECT ADDER, 303 11.1.7 OPTIMIZATION OF CARRY-SELECT ADDERS, 307 11.1.8 CARRY-LOOKAHEAD ADDERS (CLAS), 310 11.1.9 PREFIX ADDERS, 318 11.1.10 FPGA IMPLEMENTATION OF ADDERS, 322 11.1.10.1 CARRY-CHAIN ADDERS, 322 11.1.10.2 CARRY-SKIP ADDERS, 323 11.1.10.3 EXPERIMENTAL RESULTS, 326 11.1.11 LONG-OPERAND ADDERS, 327 11.1.12 MULTIOPERAND ADDERS, 328 11.1.12.1 SEQUENTIAL MULTIOPERAND ADDERS, 328 11.1.12.2 COMBINATIONAL MULTIOPERAND ADDERS, 330 CONTENTS XIII 11.1.12.3 CARRY-SAVE ADDERS, 333 11.1.12.4 PARALLEL COUNTERS, 337 11.1.13 SUBTRACTORS AND ADDER-SUBTRACTORS, 344 11.1.14 TERMINATION DETECTION, 346 11.1.15 FPGA IMPLEMENTATION OF THE TERMINATION DETECTION, 348 11.2 INTEGERS, 350 11.2.1 B S COMPLEMENT ADDERS AND SUBTRACTORS, 350 11.2.2 EXCESS-ZS ADDERS AND SUBTRACTORS, 352 11.2.3 SIGN-MAGNITUDE ADDERS AND SUBTRACTORS, 355 11.3 BIBLIOGRAPHY, 357 12 MULTIPLIERS 359 12.1 NATURAL NUMBERS, 360 12.1.1 BASIC MULTIPLIER, 360 12.1.2 SEQUENTIAL MULTIPLIERS, 363 12.1.3 CELLULAR MULTIPLIER ARRAYS, 363 12.1.3.1 RIPPLE-CARRY MULTIPLIER, 365 12.1.3.2 CARRY-SAVE MULTIPLIER, 368 12.1.3.3 FIGURES OF MERIT, 370 12.1.4 MULTIPLIERS BASED ON DISSYMMETRIC B X B S CELLS, 370 12.1.5 MULTIPLIERS BASED ON MULTIOPERAND ADDERS, 378 12.1.6 PER GELOSIA MULTIPLICATION ARRAYS, 383 12.1.6.1 INTRODUCTION, 383 12.1.6.2 ADDING TREE FOR BASE-SS PARTIAL PRODUCTS, 384 12.1.7 FPGA IMPLEMENTATION OF MULTIPLIERS, 386 12.2 INTEGERS, 388 12.2.1 SS S COMPLEMENT MULTIPLIERS, 388 12.2.2 BOOTH MULTIPLIERS, 390 12.2.2.1 BOOTH-1 MULTIPLIER, 390 12.2.2.2 BOOTH-2 MULTIPLIER, 392 12.2.2.3 SIGNED-DIGIT MULTIPLIER, 397 12.2.3 FPGA IMPLEMENTATION OF THE BOOTH-1 MULTIPLIER, 404 12.3 BIBLIOGRAPHY, 406 13 DIVIDERS 407 13.1 NATURAL NUMBERS, 407 13.2 INTEGERS, 415 13.2.1 BASE-2 NONRESTORING DIVIDER, 415 13.2.2 BASE-SS NONRESTORING DIVIDER, 421 CONTENTS 13.2.3 SRT DIVIDERS, 424 13.2.3.1 SRT-2 DIVIDER, 424 13.2.3.2 SRT-2 DIVIDER WITH CARRY-SAVE COMPUTATION OF THE REMAINDER, 428 13.2.3.3 FPGA IMPLEMENTATION OF THE CARRY-SAVE SRT-2 DIVIDER, 434 13.2.4 SRT-4 DIVIDER, 435 13.2.5 CONVERGENCE DIVIDERS, 439 13.2.5.1 NEWTON-RAPHSON DIVIDER, 439 13.2.5.2 GOLDSCHMIDT DIVIDER, 441 13.2.5.3 COMPARATIVE DATA BETWEEN NEWTON-RAPHSON (NR) AND GOLDSCHMIDT (G) IMPLEMENTATIONS, 444 13.3 BIBLIOGRAPHY, 444 OTHER ARITHMETIC OPERATORS 447 14.1 BASE CONVERSION, 447 14.1.1 GENERAL BASE CONVERSION, 447 14.1.2 BCD TO BINARY CONVERTER, 449 14.1.2.1 NONRESTORING 2 P SUBTRACTING IMPLEMENTATION, 449 14.1.2.2 SHIFT-AND-ADD BCD TO BINARY CONVERTER, 450 14.1.3 BINARY TO BCD CONVERTER, 452 14.1.4 BASE-5 TO RNS CONVERTER, 455 14.1.5 CRT RNS TO BASE-SS CONVERTER, 456 14.1.6 RNS TO MIXED-RADIX SYSTEM CONVERTER, 458 14.2 POLYNOMIAL COMPUTATION CIRCUITS, 463 14.3 LOGARITHM OPERATOR, 467 14.4 EXPONENTIAL OPERATOR, 468 14.5 SINE AND COSINE OPERATORS, 470 14.6 SQUARE ROOTERS, 472 14.6.1 RESTORING SHIFT-AND-SUBTRACT SQUARE ROOTER (NATURALS), 472 14.6.2 NONRESTORING SHIFT-AND-SUBTRACT SQUARE ROOTER (NATURALS), 475 14.6.3 NEWTON-RAPHSON SQUARE ROOTER (NATURALS), 477 14.7 BIBLIOGRAPHY, 479 CIRCUITS FOR FINITE FIELD OPERATIONS 481 15.1 OPERATIONS IN Z M , 481 15.1.1 ADDERS AND SUBTRACTORS, 481 15.1.2 MULTIPLICATION, 484 15.1.2.1 MULTIPLY AND REDUCE, 484 CONTENTS XV 15.1.2.2 SHIFTANDADD, 485 15.1.2.3 MONTGOMERY MULTIPLICATION, 487 15.1.2.4 MODULO(B*-C)REDUCTION, 490 15.1.2.5 EXPONENTIATION, 494 15.2 INVERSION IN GF(P), 497 15.3 OPERATIONS IN Z P [X]/F(X), 500 15.4 INVERSION IN GF(P ), 504 15.5 BIBLIOGRAPHY, 510 16 FLOATING-POINT UNIT 513 16.1 FLOATING-POINT SYSTEM DEFINITION, 513 16.2 ARITHMETIC OPERATIONS, 515 16.2.1 ADDITION OF POSITIVE NUMBERS, 515 16.2.2 DIFFERENCE OF POSITIVE NUMBERS, 517 16.2.3 ADDITION AND SUBTRACTION, 518 16.2.4 MULTIPLICATION, 520 16.2.5 DIVISION, 521 16.2.6 SQUARE ROOT, 522 16.3 ROUNDING SCHEMES, 524 16.4 GUARD DIGITS, 525 16.5 ADDER-SUBTRACTOR, 527 16.5.1 ALIGNMENT, 527 16.5.2 ADDITIONS, 529 16.5.3 NORMALIZATION, 530 16.5.4 ROUNDING, 530 16.6 MULTIPLIER, 537 16.7 DIVIDER, 542 16.8 SQUARE ROOT, 546 16.9 COMMENTS, 548 16.10 BIBLIOGRAPHY, 548 INDEX 549
adam_txt	SYNTHESIS OF ARITHMETIC CIRCUITS FPGA, ASIC, AND EMBEDDED SYSTEMS JEAN-PIERRE DESCHAMPS UNIVERSITY ROVIRA I VIRGILI GERY JEAN ANTOINE BIOUL NATIONAL UNIVERSITY OF THE CENTER OF THE PROVINCE OF BUENOS AIRES GUSTAVO D. SUTTER UNIVERSITY AUTONOMA OF MADRID /X^WILEY- V^TYINTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION CONTENTS PREFACE XVII ABOUT THE AUTHORS XIX 1 INTRODUCTION 1 1.1 NUMBER REPRESENTATION, 1 1.2 ALGORITHMS, 2 1.3 HARDWARE PLATFORMS, 2 1.4 HARDWARE-SOFTWARE PARTITIONING, 3 1.5 SOFTWARE GENERATION, 3 .6 SYNTHT ;SIS, 3 .7 A FIRST EXAMPLE, 3 1.7.1 1.7.2 1.7.3 1.7.4 1.7.5 1.7.6 1.7.7 1.7.8 SPECIFICATION, 3 NUMBER REPRESENTATION, 6 ALGORITHMS, 6 HARDWARE PLATFORM, 8 HARDWARE-SOFTWARE PARTITIONIN; PROGRAM GENERATION, 9 SYNTHESIS, 10 PROTOTYPE, 12 1.8 BIBLIOGRAPHY, 14 VII JJJ CONTENTS 2 MATHEMATICAL BACKGROUND 15 2.1 NUMBER THEORY, 15 2.1.1 BASIC DEFINITIONS, 15 2.1.2 EUCLIDEAN ALGORITHMS, 17 2.1.3 CONGRUENCES, 19 2.2 ALGEBRA, 25 2.2.1 CROUPS, 25 2.2.2 RINGS, 27 2.2.3 FIELDS, 27 2.2.4 POLYNOMIAL RINGS, 27 2.2.5 CONGRUENCES OF POLYNOMIAL, 32 2.3 FUNCTION APPROXIMATION, 35 2.4 BIBLIOGRAPHY, 36 3 NUMBER REPRESENTATION 39 3.1 NATURAL NUMBERS, 39 3.1.1 WEIGHTED SYSTEMS, 39 3.1.2 RESIDUE NUMBER SYSTEM, 42 3.2 INTEGERS, 42 3.2.1 SIGN-MAGNITUDE REPRESENTATION, 42 3.2.2 EXCESS-E REPRESENTATION, 43 3.2.3 5'S COMPLEMENT REPRESENTATION, 44 3.2.4 BOOTH'S ENCODING, 47 3.3 REAL NUMBERS, 51 3.4 BIBLIOGRAPHY, 54 4 ARITHMETIC OPERATIONS: ADDITION AND SUBTRACTION 55 4.1 ADDITION OF NATURAL NUMBERS, 55 4.1.1 BASIC ALGORITHM, 55 4.1.2 FASTER ALGORITHMS, 57 4.1.3 LONG-OPERAND ADDITION, 66 4.1.4 MULTIOPERAND ADDITION, 67 4.1.5 LONG-MULTIOPERAND ADDITION, 70 4.2 SUBTRACTION OF NATURAL NUMBERS, 71 4.3 INTEGERS, 71 4.3.1 SS'S COMPLEMENT ADDITION, 71 4.3.2 SS'S COMPLEMENT SIGN CHANGE, 72 4.3.3 SS'S COMPLEMENT SUBTRACTION, 74 CONTENTS IX 4.3.4 B'S COMPLEMENT OVERFLOW DETECTION, 74 4.3.5 EXCESS- ADDITION AND SUBTRACTION, 78 4.3.6 SIGN-MAGNITUDE ADDITION AND SUBTRACTION, 79 4.4 BIBLIOGRAPHY, 80 5 ARITHMETIC OPERATIONS: MULTIPLICATION 81 5.1 NATURAL NUMBERS MULTIPLICATION, 82 5.1.1 INTRODUCTION, 82 5.1.2 SHIFT AND ADD ALGORITHMS, 83 5.1.2.1 SHIFT AND ADD 1, 83 5.1.2.2 SHIFT AND ADD 2, 84 5.1.2.3 EXTENDED SHIFT AND ADD ALGORITHM: XY+C + D, 86 5.1.2.4 CELLULAR SHIFT AND ADD, 86 5.1.3 LONG-OPERAND ALGORITHM, 90 5.2 INTEGERS, 91 5.2.1 B'S COMPLEMENT MULTIPLICATION, 91 5.2.1.1 MOD B" +L " B'S COMPLEMENT MULTIPLICATION, 92 5.2.1.2 SIGNED SHIFT AND ADD, 93 5.2.1.3 POSTCORRECTION 5'S COMPLEMENT MULTIPLICATION, 93 5.2.2 POSTCORRECTION 2'S COMPLEMENT MULTIPLICATION, 96 5.2.3 BOOTH MULTIPLICATION FOR BINARY NUMBERS, 97 5.2.3.1 BOOTH-R ALGORITHMS, 97 5.2.3.2 PER GELOSIA SIGNED-DIGIT ALGORITHM, 98 5.2.4 BOOTH MULTIPLICATION FOR BASE-SS NUMBERS (BOOTH-R ALGORITHM IN BASE B), 102 5.3 SQUARING, 104 5.3.1 BASE-SS SQUARING, 104 5.3.1.1 CELLULAR CARRY-SAVE SQUARING ALGORITHM, 104 5.3.2 BASE-2 SQUARING, 106 5.4 BIBLIOGRAPHY, 107 6 ARITHMETIC OPERATIONS: DIVISION 109 6.1 NATURAL NUMBERS, 110 6.2 INTEGERS, 117 6.2.1 GENERAL ALGORITHM, 117 6.2.2 RESTORING DIVISION ALGORITHM, 121 6.2.3 BASE-2 NONRESTORING DIVISION ALGORITHM, 121 6.2.4 SRT RADIX-2 DIVISION, 126 6.2.5 SRT RADIX-2 DIVISION WITH STORED-CARRY ENCODING, 131 6.2.6 P-D DIAGRAM, 139 I CONTENTS 6.2.7 SRT-4 DIVISION, 142 6.2.8 BASE-SS NONRESTORING DIVISION ALGORITHM, 148 6.3 CONVERGENCE (FUNCTIONAL ITERATION) ALGORITHMS, 155 6.3.1 INTRODUCTION, 155 6.3.2 NEWTON-RAPHSON ITERATION TECHNIQUE, 155 6.3.3 MACLAURIN EXPANSIONGOLDSCHMIDT'S ALGORITHM, 159 6.4 BIBLIOGRAPHY, 161 7 OTHER ARITHMETIC OPERATIONS 165 7.1 BASE CONVERSION, 165 7.2 RESIDUE NUMBER SYSTEM CONVERSION, 173 7.2.1 INTRODUCTION, 173 7.2.2 BASE-SS TO RNS CONVERSION, 173 7.2.3 RNS TO BASE-SS CONVERSION, 177 7.3 LOGARITHMIC, EXPONENTIAL, AND TRIGONOMETRIE FUNCTIONS, 180 7.3.1 TAYLOR-MACLAURIN SERIES, 181 7.3.2 POLYNOMIAL APPROXIMATION, 183 7.3.3 LOGARITHM AND EXPONENTIAL FUNCTIONS APPROXIMATION BY CONVERGENCE METHODS, 184 7.3.3.1 LOGARITHM FUNCTION APPROXIMATION BY MULTIPLICATIVE NORMALIZATION, 184 7.3.3.2 EXPONENTIAL FUNCTION APPROXIMATION BY ADDITIVE NORMALIZATION, 188 7.3.4 TRIGONOMETRIE FUNCTIONSCORDIC ALGORITHMS, 194 7.4 SQUARE ROOTING, 198 7.4.1 DIGIT RECURRENCE ALGORITHMBASE-SS INTEGERS, 198 7.4.2 RESTORING BINARY SHIFT-AND-SUBTRACT SQUARE ROOTING ALGORITHM, 202 7.4.3 NONRESTORING BINARY ADD-AND-SUBTRACT SQUARE ROOTING ALGORITHM, 204 7.4.4 CONVERGENCE METHODNEWTON-RAPHSON, 208 7.5 BIBLIOGRAPHY, 208 8 FINITE FIELD OPERATIONS 211 8.1 OPERATIONS IN Z** 211 8.1.1 ADDITION, 212 8.1.2 SUBTRACTION, 213 8.1.3 MULTIPLICATION, 213 8.1.3.1 MULTIPLY AND REDUCE, 214 8.1.3.2 MODIFIED SHIFT-AND-ADD ALGORITHM, 214 CONTENTS XI 8.1.3.3 MONTGOMERY MULTIPLICATION, 216 8.1.3.4 SPECIFIC RING, 220 8.1.4 EXPONENTIATION, 221 8.2 OPERATIONS IN GF(P), 222 8.3 OPERATIONS IN Z P \X]/F(X), 224 8.3.1 ADDITION AND SUBTRACTION, 224 8.3.2 MULTIPLICATION, 225 8.4 OPERATIONS IN GF(P"), 228 8.5 BIBLIOGRAPHY, 236 APPENDIX 8.1 COMPUTATION OFF KI , 236 9 HARDWARE PLATFORMS 239 9.1 DESIGN METHODS FOR ELECTRONIC SYSTEMS, 239 9.1.1 BASIC BLOCKS OF INTEGRATED SYSTEMS, 240 9.1.2 RECURRING TOPICS IN ELECTRONIC DESIGN, 241 9.1.2.1 DESIGN CHALLENGE: OPTIMIZING DESIGN METRICS, 241 9.1.2.2 COST IN INTEGRATED CIRCUITS, 242 9.1.2.3 MOORE'S LAW, 243 9.1.2.4 TIME-TO-MARKET, 243 9.1.2.5 PERFORMANCE METRIE, 244 9.1.2.6 THE POWER DIMENSION, 245 9.2 INSTRUCTION SET PROCESSORS, 245 9.2.1 MICROPROCESSORS, 247 9.2.2 MICROCONTROLLERS, 248 9.2.3 EMBEDDED PROCESSORS EVERYWHERE, 248 9.2.4 DIGITAL SIGNAL PROCESSORS, 249 9.2.5 APPLICATION-SPECIFIC INSTRUCTION SET PROCESSORS, 250 9.2.6 PROGRAMMING INSTRUCTION SET PROCESSORS, 251 9.3 ASIC DESIGNS, 252 9.3.1 FULL-CUSTOM ASIC, 252 9.3.2 SEMICUSTOM ASIC, 253 9.3.2.1 GATE-ARRAY ASIC, 253 9.3.2.2 STANDARD-CELL-BASED ASIC, 254 9.3.3 DESIGN FLOW IN ASIC, 255 9.4 PROGRAMMABLE LOGIC, 256 9.4.1 PROGRAMMABLE LOGIC DEVICES (PLDS), 256 9.4.2 FIELD PROGRAMMABLE GATE ARRAY (FPGA), 258 9.4.2.1 WHY FPGA? A SHORT HISTORICAL SURVEY, 258 9.4.2.2 BASIC FPGA CONCEPTS, 258 XII CONTENTS 9.4.3 XILINX* SPECIFICS, 260 9.4.3.1 CONFIGURABLE LOGIC BLOCKS (CLBS), 262 9.4.3.2 INPUT/OUTPUT BLOCKS (IOBS), 262 9.4.3.3 RAM BLOCKS, 262 9.4.3.4 PROGRAMMABLE ROUTING, 264 9.4.3.5 ARITHMETIC RESOURCES IN XILINX FPGAS, 264 9.4.4 FPGA GENERIC DESIGN FLOW, 264 9.5 HARDWARE DESCRIPTION LANGUAGES (HDLS), 267 9.5.1 TODAY'S AND TOMORROW'S HDLS, 267 9.6 FURTHER READINGS, 268 9.7 BIBLIOGRAPHY, 268 10 CIRCUIT SYNTHESIS: GENERAL PRINCIPLES 271 10.1 RESOURCES, 272 10.2 PRECEDENCE RELATION AND SCHEDULING, 277 10.3 PIPELINE, 281 10.4 SELF-TIMED CIRCUITS, 282 10.5 BIBLIOGRAPHY, 288 11 ADDERS AND SUBTRACTORS 289 11.1 NATURAL NUMBERS, 289 11.1.1 BASIC ADDER (RIPPLE-CARRY ADDER), 289 11.1.2 CARRY-CHAIN ADDER, 292 11.1.3 CARRY-SKIP ADDER, 294 11.1.4 OPTIMIZATION OF CARRY-SKIP ADDERS, 298 11.1.5 BASE-SS V ADDER, 301 11.1.6 CARRY-SELECT ADDER, 303 11.1.7 OPTIMIZATION OF CARRY-SELECT ADDERS, 307 11.1.8 CARRY-LOOKAHEAD ADDERS (CLAS), 310 11.1.9 PREFIX ADDERS, 318 11.1.10 FPGA IMPLEMENTATION OF ADDERS, 322 11.1.10.1 CARRY-CHAIN ADDERS, 322 11.1.10.2 CARRY-SKIP ADDERS, 323 11.1.10.3 EXPERIMENTAL RESULTS, 326 11.1.11 LONG-OPERAND ADDERS, 327 11.1.12 MULTIOPERAND ADDERS, 328 11.1.12.1 SEQUENTIAL MULTIOPERAND ADDERS, 328 11.1.12.2 COMBINATIONAL MULTIOPERAND ADDERS, 330 CONTENTS XIII 11.1.12.3 CARRY-SAVE ADDERS, 333 11.1.12.4 PARALLEL COUNTERS, 337 11.1.13 SUBTRACTORS AND ADDER-SUBTRACTORS, 344 11.1.14 TERMINATION DETECTION, 346 11.1.15 FPGA IMPLEMENTATION OF THE TERMINATION DETECTION, 348 11.2 INTEGERS, 350 11.2.1 B'S COMPLEMENT ADDERS AND SUBTRACTORS, 350 11.2.2 EXCESS-ZS ADDERS AND SUBTRACTORS, 352 11.2.3 SIGN-MAGNITUDE ADDERS AND SUBTRACTORS, 355 11.3 BIBLIOGRAPHY, 357 12 MULTIPLIERS 359 12.1 NATURAL NUMBERS, 360 12.1.1 BASIC MULTIPLIER, 360 12.1.2 SEQUENTIAL MULTIPLIERS, 363 12.1.3 CELLULAR MULTIPLIER ARRAYS, 363 12.1.3.1 RIPPLE-CARRY MULTIPLIER, 365 12.1.3.2 CARRY-SAVE MULTIPLIER, 368 12.1.3.3 FIGURES OF MERIT, 370 12.1.4 MULTIPLIERS BASED ON DISSYMMETRIC B' X B S CELLS, 370 12.1.5 MULTIPLIERS BASED ON MULTIOPERAND ADDERS, 378 12.1.6 PER GELOSIA MULTIPLICATION ARRAYS, 383 12.1.6.1 INTRODUCTION, 383 12.1.6.2 ADDING TREE FOR BASE-SS PARTIAL PRODUCTS, 384 12.1.7 FPGA IMPLEMENTATION OF MULTIPLIERS, 386 12.2 INTEGERS, 388 12.2.1 SS'S COMPLEMENT MULTIPLIERS, 388 12.2.2 BOOTH MULTIPLIERS, 390 12.2.2.1 BOOTH-1 MULTIPLIER, 390 12.2.2.2 BOOTH-2 MULTIPLIER, 392 12.2.2.3 SIGNED-DIGIT MULTIPLIER, 397 12.2.3 FPGA IMPLEMENTATION OF THE BOOTH-1 MULTIPLIER, 404 12.3 BIBLIOGRAPHY, 406 13 DIVIDERS 407 13.1 NATURAL NUMBERS, 407 13.2 INTEGERS, 415 13.2.1 BASE-2 NONRESTORING DIVIDER, 415 13.2.2 BASE-SS NONRESTORING DIVIDER, 421 CONTENTS 13.2.3 SRT DIVIDERS, 424 13.2.3.1 SRT-2 DIVIDER, 424 13.2.3.2 SRT-2 DIVIDER WITH CARRY-SAVE COMPUTATION OF THE REMAINDER, 428 13.2.3.3 FPGA IMPLEMENTATION OF THE CARRY-SAVE SRT-2 DIVIDER, 434 13.2.4 SRT-4 DIVIDER, 435 13.2.5 CONVERGENCE DIVIDERS, 439 13.2.5.1 NEWTON-RAPHSON DIVIDER, 439 13.2.5.2 GOLDSCHMIDT DIVIDER, 441 13.2.5.3 COMPARATIVE DATA BETWEEN NEWTON-RAPHSON (NR) AND GOLDSCHMIDT (G) IMPLEMENTATIONS, 444 13.3 BIBLIOGRAPHY, 444 OTHER ARITHMETIC OPERATORS 447 14.1 BASE CONVERSION, 447 14.1.1 GENERAL BASE CONVERSION, 447 14.1.2 BCD TO BINARY CONVERTER, 449 14.1.2.1 NONRESTORING 2 P SUBTRACTING IMPLEMENTATION, 449 14.1.2.2 SHIFT-AND-ADD BCD TO BINARY CONVERTER, 450 14.1.3 BINARY TO BCD CONVERTER, 452 14.1.4 BASE-5 TO RNS CONVERTER, 455 14.1.5 CRT RNS TO BASE-SS CONVERTER, 456 14.1.6 RNS TO MIXED-RADIX SYSTEM CONVERTER, 458 14.2 POLYNOMIAL COMPUTATION CIRCUITS, 463 14.3 LOGARITHM OPERATOR, 467 14.4 EXPONENTIAL OPERATOR, 468 14.5 SINE AND COSINE OPERATORS, 470 14.6 SQUARE ROOTERS, 472 14.6.1 RESTORING SHIFT-AND-SUBTRACT SQUARE ROOTER (NATURALS), 472 14.6.2 NONRESTORING SHIFT-AND-SUBTRACT SQUARE ROOTER (NATURALS), 475 14.6.3 NEWTON-RAPHSON SQUARE ROOTER (NATURALS), 477 14.7 BIBLIOGRAPHY, 479 CIRCUITS FOR FINITE FIELD OPERATIONS 481 15.1 OPERATIONS IN Z M , 481 15.1.1 ADDERS AND SUBTRACTORS, 481 15.1.2 MULTIPLICATION, 484 15.1.2.1 MULTIPLY AND REDUCE, 484 CONTENTS XV 15.1.2.2 SHIFTANDADD, 485 15.1.2.3 MONTGOMERY MULTIPLICATION, 487 15.1.2.4 MODULO(B*-C)REDUCTION, 490 15.1.2.5 EXPONENTIATION, 494 15.2 INVERSION IN GF(P), 497 15.3 OPERATIONS IN Z P [X]/F(X), 500 15.4 INVERSION IN GF(P"), 504 15.5 BIBLIOGRAPHY, 510 16 FLOATING-POINT UNIT 513 16.1 FLOATING-POINT SYSTEM DEFINITION, 513 16.2 ARITHMETIC OPERATIONS, 515 16.2.1 ADDITION OF POSITIVE NUMBERS, 515 16.2.2 DIFFERENCE OF POSITIVE NUMBERS, 517 16.2.3 ADDITION AND SUBTRACTION, 518 16.2.4 MULTIPLICATION, 520 16.2.5 DIVISION, 521 16.2.6 SQUARE ROOT, 522 16.3 ROUNDING SCHEMES, 524 16.4 GUARD DIGITS, 525 16.5 ADDER-SUBTRACTOR, 527 16.5.1 ALIGNMENT, 527 16.5.2 ADDITIONS, 529 16.5.3 NORMALIZATION, 530 16.5.4 ROUNDING, 530 16.6 MULTIPLIER, 537 16.7 DIVIDER, 542 16.8 SQUARE ROOT, 546 16.9 COMMENTS, 548 16.10 BIBLIOGRAPHY, 548 INDEX 549
any_adam_object	1
any_adam_object_boolean	1
author	Deschamps, Jean-Pierre Bioul, Géry Jean Antoine Sutter, Gustavo D.
author_facet	Deschamps, Jean-Pierre Bioul, Géry Jean Antoine Sutter, Gustavo D.
author_role	aut aut aut
author_sort	Deschamps, Jean-Pierre
author_variant	j p d jpd g j a b gja gjab g d s gd gds
building	Verbundindex
bvnumber	BV023091889
callnumber-first	T - Technology
callnumber-label	TK7895
callnumber-raw	TK7895.A65
callnumber-search	TK7895.A65
callnumber-sort	TK 47895 A65
callnumber-subject	TK - Electrical and Nuclear Engineering
classification_rvk	ST 125 ST 150 ZN 4940
ctrlnum	(OCoLC)254061216 (DE-599)BVBBV023091889
dewey-full	621.39/5
dewey-hundreds	600 - Technology (Applied sciences)
dewey-ones	621 - Applied physics
dewey-raw	621.39/5
dewey-search	621.39/5
dewey-sort	3621.39 15
dewey-tens	620 - Engineering and allied operations
discipline	Informatik Elektrotechnik / Elektronik / Nachrichtentechnik
discipline_str_mv	Informatik Elektrotechnik / Elektronik / Nachrichtentechnik
format	Book
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02328nam a2200541zc 4500</leader><controlfield tag="001">BV023091889</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20100209 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">080122s2006 xxuad\|\| \|\|\|\| 00\|\|\| eng d</controlfield><datafield tag="010" ind1=" " ind2=" "><subfield code="a">2005003237</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780471687832</subfield><subfield code="9">978-0-471-68783-2</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0471687839</subfield><subfield code="c">cloth</subfield><subfield code="9">0-471-68783-9</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)254061216</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV023091889</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">xxu</subfield><subfield code="c">US</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-706</subfield><subfield code="a">DE-573</subfield><subfield code="a">DE-83</subfield><subfield code="a">DE-Aug4</subfield><subfield code="a">DE-29T</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7895.A65</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 125</subfield><subfield code="0">(DE-625)143586:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 150</subfield><subfield code="0">(DE-625)143594:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4940</subfield><subfield code="0">(DE-625)157423:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Deschamps, Jean-Pierre</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Synthesis of arithmetic circuits</subfield><subfield code="b">FPGA, ASIC and embedded systems</subfield><subfield code="c">Jean-Pierre Deschamps ; Géry Jean Antoine Bioul ; Gustavo D. Sutter</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Hoboken, N.J.</subfield><subfield code="b">Wiley</subfield><subfield code="c">2006</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XIX, 556 S.</subfield><subfield code="b">Ill., graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer arithmetic and logic units</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Digital electronics</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Embedded computer systems</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Computerarithmetik</subfield><subfield code="0">(DE-588)4135485-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Eingebettetes System</subfield><subfield code="0">(DE-588)4396978-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitalelektronik</subfield><subfield code="0">(DE-588)4260328-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Digitalelektronik</subfield><subfield code="0">(DE-588)4260328-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Computerarithmetik</subfield><subfield code="0">(DE-588)4135485-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Eingebettetes System</subfield><subfield code="0">(DE-588)4396978-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Bioul, Géry Jean Antoine</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Sutter, Gustavo D.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://www.loc.gov/catdir/toc/ecip057/2005003237.html</subfield><subfield code="3">Table of contents only</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://www.loc.gov/catdir/enhancements/fy0621/2005003237-b.html</subfield><subfield code="3">Contributor biographical information</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://www.loc.gov/catdir/enhancements/fy0621/2005003237-d.html</subfield><subfield code="3">Publisher description</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">GBV Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016294746&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-016294746</subfield></datafield></record></collection>
id	DE-604.BV023091889
illustrated	Illustrated
index_date	2024-07-02T19:41:21Z
indexdate	2024-07-09T21:10:49Z
institution	BVB
isbn	9780471687832 0471687839
language	English
lccn	2005003237
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-016294746
oclc_num	254061216
open_access_boolean
owner	DE-706 DE-573 DE-83 DE-Aug4 DE-29T
owner_facet	DE-706 DE-573 DE-83 DE-Aug4 DE-29T
physical	XIX, 556 S. Ill., graph. Darst.
publishDate	2006
publishDateSearch	2006
publishDateSort	2006
publisher	Wiley
record_format	marc
spelling	Deschamps, Jean-Pierre Verfasser aut Synthesis of arithmetic circuits FPGA, ASIC and embedded systems Jean-Pierre Deschamps ; Géry Jean Antoine Bioul ; Gustavo D. Sutter Hoboken, N.J. Wiley 2006 XIX, 556 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Computer arithmetic and logic units Digital electronics Embedded computer systems Computerarithmetik (DE-588)4135485-0 gnd rswk-swf Eingebettetes System (DE-588)4396978-1 gnd rswk-swf Digitalelektronik (DE-588)4260328-6 gnd rswk-swf Digitalelektronik (DE-588)4260328-6 s Computerarithmetik (DE-588)4135485-0 s Eingebettetes System (DE-588)4396978-1 s DE-604 Bioul, Géry Jean Antoine Verfasser aut Sutter, Gustavo D. Verfasser aut http://www.loc.gov/catdir/toc/ecip057/2005003237.html Table of contents only http://www.loc.gov/catdir/enhancements/fy0621/2005003237-b.html Contributor biographical information http://www.loc.gov/catdir/enhancements/fy0621/2005003237-d.html Publisher description GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016294746&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Deschamps, Jean-Pierre Bioul, Géry Jean Antoine Sutter, Gustavo D. Synthesis of arithmetic circuits FPGA, ASIC and embedded systems Computer arithmetic and logic units Digital electronics Embedded computer systems Computerarithmetik (DE-588)4135485-0 gnd Eingebettetes System (DE-588)4396978-1 gnd Digitalelektronik (DE-588)4260328-6 gnd
subject_GND	(DE-588)4135485-0 (DE-588)4396978-1 (DE-588)4260328-6
title	Synthesis of arithmetic circuits FPGA, ASIC and embedded systems
title_auth	Synthesis of arithmetic circuits FPGA, ASIC and embedded systems
title_exact_search	Synthesis of arithmetic circuits FPGA, ASIC and embedded systems
title_exact_search_txtP	Synthesis of arithmetic circuits FPGA, ASIC and embedded systems
title_full	Synthesis of arithmetic circuits FPGA, ASIC and embedded systems Jean-Pierre Deschamps ; Géry Jean Antoine Bioul ; Gustavo D. Sutter
title_fullStr	Synthesis of arithmetic circuits FPGA, ASIC and embedded systems Jean-Pierre Deschamps ; Géry Jean Antoine Bioul ; Gustavo D. Sutter
title_full_unstemmed	Synthesis of arithmetic circuits FPGA, ASIC and embedded systems Jean-Pierre Deschamps ; Géry Jean Antoine Bioul ; Gustavo D. Sutter
title_short	Synthesis of arithmetic circuits
title_sort	synthesis of arithmetic circuits fpga asic and embedded systems
title_sub	FPGA, ASIC and embedded systems
topic	Computer arithmetic and logic units Digital electronics Embedded computer systems Computerarithmetik (DE-588)4135485-0 gnd Eingebettetes System (DE-588)4396978-1 gnd Digitalelektronik (DE-588)4260328-6 gnd
topic_facet	Computer arithmetic and logic units Digital electronics Embedded computer systems Computerarithmetik Eingebettetes System Digitalelektronik
url	http://www.loc.gov/catdir/toc/ecip057/2005003237.html http://www.loc.gov/catdir/enhancements/fy0621/2005003237-b.html http://www.loc.gov/catdir/enhancements/fy0621/2005003237-d.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016294746&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT deschampsjeanpierre synthesisofarithmeticcircuitsfpgaasicandembeddedsystems AT bioulgeryjeanantoine synthesisofarithmeticcircuitsfpgaasicandembeddedsystems AT suttergustavod synthesisofarithmeticcircuitsfpgaasicandembeddedsystems

Verfügbarkeit

Es ist kein Print-Exemplar vorhanden.

Fernleihe Bestellen Achtung: Nicht im THWS-Bestand! Inhaltsverzeichnis

MARC

Datensatz im Suchindex

Es ist kein Print-Exemplar vorhanden.

Ähnliche Einträge