Scaling shared-bus multiprocessors with multiple busses and shared caches: a performance study
Abstract: "The main limitation of shared-bus multiprocessors is that the common bus tends to be the primary source for contention, and thus imposes a limit on the number of processors in the system. Alternate architectural features are necessary to reduce the memory bandwidth demands and to inc...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Seattle, Wash.
1991
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| Schriftenreihe: | University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report
91,9,4 |
| Schlagworte: | |
| Zusammenfassung: | Abstract: "The main limitation of shared-bus multiprocessors is that the common bus tends to be the primary source for contention, and thus imposes a limit on the number of processors in the system. Alternate architectural features are necessary to reduce the memory bandwidth demands and to increase the bus bandwidth. In this paper, we investigate the cost-performance effects of two enhancements: higher bus transaction rates, e.g., through the use of multiple busses, and shared two-level caches. The performance figures are obtained via simulation with loads derived from traces of real applications, some of which show a significant skew in the distribution of memory bank access. A new multiple bus scheme, called multiple interleaved busses, is described and analyzed This scheme is a generalization of previous approaches, and attempts to balance performance and cost tradeoffs in a snoopy-cache multiprocessor environment. The results from simulation show that multiple interleaved busses perform almost as well as multiple independent busses, but with simpler and less costly implementation. Furthermore, multiple interleaved busses are shown to deliver much better performance than interleaved busses when the skew of accesses across the interleaves is large. Shared second-level caches have been shown to be very effective in the design space under consideration. Such systems might offer considerable implementation economies with relatively small design cost We show that depending on the design point in question, bus operation buffers might be useful in shared second level caches by reducing the effects of high skew and greater multiprocessing level. With the presence of these buffers, the uses of shared caches resulted in only a small throughput degradation. |
| Beschreibung: | 22 S. |
Internformat
MARC
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| 100 | 1 | |a Bertoni, Jonathan |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Scaling shared-bus multiprocessors with multiple busses and shared caches |b a performance study |c Jonathan Bertoni ; Jean-Loup Baer ; Wen-Hann Wang |
| 264 | 1 | |a Seattle, Wash. |c 1991 | |
| 300 | |a 22 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report |v 91,9,4 | |
| 520 | 3 | |a Abstract: "The main limitation of shared-bus multiprocessors is that the common bus tends to be the primary source for contention, and thus imposes a limit on the number of processors in the system. Alternate architectural features are necessary to reduce the memory bandwidth demands and to increase the bus bandwidth. In this paper, we investigate the cost-performance effects of two enhancements: higher bus transaction rates, e.g., through the use of multiple busses, and shared two-level caches. The performance figures are obtained via simulation with loads derived from traces of real applications, some of which show a significant skew in the distribution of memory bank access. A new multiple bus scheme, called multiple interleaved busses, is described and analyzed | |
| 520 | 3 | |a This scheme is a generalization of previous approaches, and attempts to balance performance and cost tradeoffs in a snoopy-cache multiprocessor environment. The results from simulation show that multiple interleaved busses perform almost as well as multiple independent busses, but with simpler and less costly implementation. Furthermore, multiple interleaved busses are shown to deliver much better performance than interleaved busses when the skew of accesses across the interleaves is large. Shared second-level caches have been shown to be very effective in the design space under consideration. Such systems might offer considerable implementation economies with relatively small design cost | |
| 520 | 3 | |a We show that depending on the design point in question, bus operation buffers might be useful in shared second level caches by reducing the effects of high skew and greater multiprocessing level. With the presence of these buffers, the uses of shared caches resulted in only a small throughput degradation. | |
| 650 | 4 | |a Multiprocessors | |
| 700 | 1 | |a Baer, Jean-Loup |e Verfasser |4 aut | |
| 700 | 1 | |a Wang, Wen-Hann |e Verfasser |4 aut | |
| 810 | 2 | |a Department of Computer Science: Technical report |t University of Washington <Seattle, Wash.> |v 91,9,4 |w (DE-604)BV008930431 |9 91,9,4 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-005961128 | ||
Datensatz im Suchindex
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| any_adam_object | |
| author | Bertoni, Jonathan Baer, Jean-Loup Wang, Wen-Hann |
| author_facet | Bertoni, Jonathan Baer, Jean-Loup Wang, Wen-Hann |
| author_role | aut aut aut |
| author_sort | Bertoni, Jonathan |
| author_variant | j b jb j l b jlb w h w whw |
| building | Verbundindex |
| bvnumber | BV009015553 |
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| format | Book |
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| id | DE-604.BV009015553 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T17:28:36Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-005961128 |
| oclc_num | 28390720 |
| open_access_boolean | |
| owner | DE-29T |
| owner_facet | DE-29T |
| physical | 22 S. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| record_format | marc |
| series2 | University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report |
| spelling | Bertoni, Jonathan Verfasser aut Scaling shared-bus multiprocessors with multiple busses and shared caches a performance study Jonathan Bertoni ; Jean-Loup Baer ; Wen-Hann Wang Seattle, Wash. 1991 22 S. txt rdacontent n rdamedia nc rdacarrier University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report 91,9,4 Abstract: "The main limitation of shared-bus multiprocessors is that the common bus tends to be the primary source for contention, and thus imposes a limit on the number of processors in the system. Alternate architectural features are necessary to reduce the memory bandwidth demands and to increase the bus bandwidth. In this paper, we investigate the cost-performance effects of two enhancements: higher bus transaction rates, e.g., through the use of multiple busses, and shared two-level caches. The performance figures are obtained via simulation with loads derived from traces of real applications, some of which show a significant skew in the distribution of memory bank access. A new multiple bus scheme, called multiple interleaved busses, is described and analyzed This scheme is a generalization of previous approaches, and attempts to balance performance and cost tradeoffs in a snoopy-cache multiprocessor environment. The results from simulation show that multiple interleaved busses perform almost as well as multiple independent busses, but with simpler and less costly implementation. Furthermore, multiple interleaved busses are shown to deliver much better performance than interleaved busses when the skew of accesses across the interleaves is large. Shared second-level caches have been shown to be very effective in the design space under consideration. Such systems might offer considerable implementation economies with relatively small design cost We show that depending on the design point in question, bus operation buffers might be useful in shared second level caches by reducing the effects of high skew and greater multiprocessing level. With the presence of these buffers, the uses of shared caches resulted in only a small throughput degradation. Multiprocessors Baer, Jean-Loup Verfasser aut Wang, Wen-Hann Verfasser aut Department of Computer Science: Technical report University of Washington <Seattle, Wash.> 91,9,4 (DE-604)BV008930431 91,9,4 |
| spellingShingle | Bertoni, Jonathan Baer, Jean-Loup Wang, Wen-Hann Scaling shared-bus multiprocessors with multiple busses and shared caches a performance study Multiprocessors |
| title | Scaling shared-bus multiprocessors with multiple busses and shared caches a performance study |
| title_auth | Scaling shared-bus multiprocessors with multiple busses and shared caches a performance study |
| title_exact_search | Scaling shared-bus multiprocessors with multiple busses and shared caches a performance study |
| title_full | Scaling shared-bus multiprocessors with multiple busses and shared caches a performance study Jonathan Bertoni ; Jean-Loup Baer ; Wen-Hann Wang |
| title_fullStr | Scaling shared-bus multiprocessors with multiple busses and shared caches a performance study Jonathan Bertoni ; Jean-Loup Baer ; Wen-Hann Wang |
| title_full_unstemmed | Scaling shared-bus multiprocessors with multiple busses and shared caches a performance study Jonathan Bertoni ; Jean-Loup Baer ; Wen-Hann Wang |
| title_short | Scaling shared-bus multiprocessors with multiple busses and shared caches |
| title_sort | scaling shared bus multiprocessors with multiple busses and shared caches a performance study |
| title_sub | a performance study |
| topic | Multiprocessors |
| topic_facet | Multiprocessors |
| volume_link | (DE-604)BV008930431 |
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