Quick turnaround ASIC design in VHDL: core-based behavioral synthesis
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | Undetermined |
| Veröffentlicht: |
Boston [u.a.]
Kluwer
1996
|
| Schriftenreihe: | The Kluwer international series in engineering and computer science
367 |
| Schlagworte: | |
| Beschreibung: | XVIII, 180 S. Ill., graph. Darst. |
| ISBN: | 0792397444 |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV011113075 | ||
| 003 | DE-604 | ||
| 005 | 19970414 | ||
| 007 | t | ||
| 008 | 961213s1996 ad|| |||| 00||| undod | ||
| 020 | |a 0792397444 |9 0-7923-9744-4 | ||
| 035 | |a (OCoLC)246512557 | ||
| 035 | |a (DE-599)BVBBV011113075 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | |a und | ||
| 049 | |a DE-91 |a DE-91G | ||
| 084 | |a ELT 360f |2 stub | ||
| 084 | |a DAT 190f |2 stub | ||
| 100 | 1 | |a BenRomdhane, Mohamed S. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Quick turnaround ASIC design in VHDL |b core-based behavioral synthesis |c Mohamed S. Ben Romdhane ; Vijay K. Madisetti ; John W. Hines |
| 246 | 1 | 3 | |a Quick-turnaround ASIC design in VHDL |
| 264 | 1 | |a Boston [u.a.] |b Kluwer |c 1996 | |
| 300 | |a XVIII, 180 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a The Kluwer international series in engineering and computer science |v 367 | |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |D s |
| 689 | 0 | 1 | |a Entwurf |0 (DE-588)4121208-3 |D s |
| 689 | 0 | 2 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Madisetti, Vijay K. |e Verfasser |4 aut | |
| 700 | 1 | |a Hines, John W. |e Verfasser |4 aut | |
| 830 | 0 | |a The Kluwer international series in engineering and computer science |v 367 |w (DE-604)BV023545171 |9 367 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-007446214 | ||
Datensatz im Suchindex
| _version_ | 1804125604798267392 |
|---|---|
| any_adam_object | |
| author | BenRomdhane, Mohamed S. Madisetti, Vijay K. Hines, John W. |
| author_facet | BenRomdhane, Mohamed S. Madisetti, Vijay K. Hines, John W. |
| author_role | aut aut aut |
| author_sort | BenRomdhane, Mohamed S. |
| author_variant | m s b ms msb v k m vk vkm j w h jw jwh |
| building | Verbundindex |
| bvnumber | BV011113075 |
| classification_tum | ELT 360f DAT 190f |
| ctrlnum | (OCoLC)246512557 (DE-599)BVBBV011113075 |
| discipline | Informatik Elektrotechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01603nam a2200421 cb4500</leader><controlfield tag="001">BV011113075</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">19970414 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">961213s1996 ad|| |||| 00||| undod</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0792397444</subfield><subfield code="9">0-7923-9744-4</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)246512557</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV011113075</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">und</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield><subfield code="a">DE-91G</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 360f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 190f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">BenRomdhane, Mohamed S.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Quick turnaround ASIC design in VHDL</subfield><subfield code="b">core-based behavioral synthesis</subfield><subfield code="c">Mohamed S. Ben Romdhane ; Vijay K. Madisetti ; John W. Hines</subfield></datafield><datafield tag="246" ind1="1" ind2="3"><subfield code="a">Quick-turnaround ASIC design in VHDL</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston [u.a.]</subfield><subfield code="b">Kluwer</subfield><subfield code="c">1996</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XVIII, 180 S.</subfield><subfield code="b">Ill., graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">The Kluwer international series in engineering and computer science</subfield><subfield code="v">367</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Kundenspezifische Schaltung</subfield><subfield code="0">(DE-588)4122250-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Kundenspezifische Schaltung</subfield><subfield code="0">(DE-588)4122250-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Madisetti, Vijay K.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Hines, John W.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">The Kluwer international series in engineering and computer science</subfield><subfield code="v">367</subfield><subfield code="w">(DE-604)BV023545171</subfield><subfield code="9">367</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-007446214</subfield></datafield></record></collection> |
| id | DE-604.BV011113075 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T18:04:12Z |
| institution | BVB |
| isbn | 0792397444 |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007446214 |
| oclc_num | 246512557 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-91G DE-BY-TUM |
| owner_facet | DE-91 DE-BY-TUM DE-91G DE-BY-TUM |
| physical | XVIII, 180 S. Ill., graph. Darst. |
| publishDate | 1996 |
| publishDateSearch | 1996 |
| publishDateSort | 1996 |
| publisher | Kluwer |
| record_format | marc |
| series | The Kluwer international series in engineering and computer science |
| series2 | The Kluwer international series in engineering and computer science |
| spelling | BenRomdhane, Mohamed S. Verfasser aut Quick turnaround ASIC design in VHDL core-based behavioral synthesis Mohamed S. Ben Romdhane ; Vijay K. Madisetti ; John W. Hines Quick-turnaround ASIC design in VHDL Boston [u.a.] Kluwer 1996 XVIII, 180 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier The Kluwer international series in engineering and computer science 367 VHDL (DE-588)4254792-1 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 s Entwurf (DE-588)4121208-3 s VHDL (DE-588)4254792-1 s DE-604 Madisetti, Vijay K. Verfasser aut Hines, John W. Verfasser aut The Kluwer international series in engineering and computer science 367 (DE-604)BV023545171 367 |
| spellingShingle | BenRomdhane, Mohamed S. Madisetti, Vijay K. Hines, John W. Quick turnaround ASIC design in VHDL core-based behavioral synthesis The Kluwer international series in engineering and computer science VHDL (DE-588)4254792-1 gnd Entwurf (DE-588)4121208-3 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| subject_GND | (DE-588)4254792-1 (DE-588)4121208-3 (DE-588)4122250-7 |
| title | Quick turnaround ASIC design in VHDL core-based behavioral synthesis |
| title_alt | Quick-turnaround ASIC design in VHDL |
| title_auth | Quick turnaround ASIC design in VHDL core-based behavioral synthesis |
| title_exact_search | Quick turnaround ASIC design in VHDL core-based behavioral synthesis |
| title_full | Quick turnaround ASIC design in VHDL core-based behavioral synthesis Mohamed S. Ben Romdhane ; Vijay K. Madisetti ; John W. Hines |
| title_fullStr | Quick turnaround ASIC design in VHDL core-based behavioral synthesis Mohamed S. Ben Romdhane ; Vijay K. Madisetti ; John W. Hines |
| title_full_unstemmed | Quick turnaround ASIC design in VHDL core-based behavioral synthesis Mohamed S. Ben Romdhane ; Vijay K. Madisetti ; John W. Hines |
| title_short | Quick turnaround ASIC design in VHDL |
| title_sort | quick turnaround asic design in vhdl core based behavioral synthesis |
| title_sub | core-based behavioral synthesis |
| topic | VHDL (DE-588)4254792-1 gnd Entwurf (DE-588)4121208-3 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| topic_facet | VHDL Entwurf Kundenspezifische Schaltung |
| volume_link | (DE-604)BV023545171 |
| work_keys_str_mv | AT benromdhanemohameds quickturnaroundasicdesigninvhdlcorebasedbehavioralsynthesis AT madisettivijayk quickturnaroundasicdesigninvhdlcorebasedbehavioralsynthesis AT hinesjohnw quickturnaroundasicdesigninvhdlcorebasedbehavioralsynthesis AT benromdhanemohameds quickturnaroundasicdesigninvhdl AT madisettivijayk quickturnaroundasicdesigninvhdl AT hinesjohnw quickturnaroundasicdesigninvhdl |